Nokia 9110 Service Manual
PAMS
Technical Documentation
RAE–2
BS1
Page 5 – 22
Section 02/99
rechargeable. It is charged by the Phaser VBACK regulator using 0.5mA
current when the main battery is connected.
current when the main battery is connected.
Reset and power management
The Phaser is connected to the I/O space of the H3 by using a 7 bit wide
data bus and a 3 bit wide address bus. The BS2 PDAPWRU on the PDA
board supplies two different voltage levels to the system;
2.85V is used as the main operating voltage for all circuits and
about 19V that is needed for the LCD bias (V17). The LCD bias voltage is
used to adjust the contrast ratio of the LCD screen. The LCD bias volt-
age is controlled by the Phaser ASIC.
data bus and a 3 bit wide address bus. The BS2 PDAPWRU on the PDA
board supplies two different voltage levels to the system;
2.85V is used as the main operating voltage for all circuits and
about 19V that is needed for the LCD bias (V17). The LCD bias voltage is
used to adjust the contrast ratio of the LCD screen. The LCD bias volt-
age is controlled by the Phaser ASIC.
The V17 and V28_1 ON/OFF are switched by the Phaser, but optionally
also the CPU can control these signals directly with HW means, indepen-
dently of the SW controlled register settings. The phaser provides also
the POWERGOOD signal for the CPU. The system reset circuit is part of
the power supply. When the battery voltage is higher than 3.4V a
PWRGOOD is generated for the CPU. The reset circuit also asserts the
reset signal whenever the Vcc supply voltage declines below the thresh-
old, keeping it asserted for at least 50ms after Vcc has risen above the
reset threshold. The reset circuit is designed to ignore fast transients
(t < 64
also the CPU can control these signals directly with HW means, indepen-
dently of the SW controlled register settings. The phaser provides also
the POWERGOOD signal for the CPU. The system reset circuit is part of
the power supply. When the battery voltage is higher than 3.4V a
PWRGOOD is generated for the CPU. The reset circuit also asserts the
reset signal whenever the Vcc supply voltage declines below the thresh-
old, keeping it asserted for at least 50ms after Vcc has risen above the
reset threshold. The reset circuit is designed to ignore fast transients
(t < 64
µ
s) in Vcc.
There is an undervoltage lockout (UVLO) block inside the Phaser. Below
the threshold limit the comparator shuts down all Phaser functionality to
prevent the battery from overdischarge. Otherwise the VSYS regulator
current drains the battery when left unused for long period. After the
UVLO there is only reference block in the Phaser drawing current from
the battery. The UVLO has a little hysteresis and is cancelled when the
battery voltage has risen to 2.7V. However, reset to the CPU is given only
when battery voltage rises to 3.45V. This in order to avoid unsuccessful
power–ups. When the lockout voltage level is reached, the battery volt-
age rises because the load is removed.
the threshold limit the comparator shuts down all Phaser functionality to
prevent the battery from overdischarge. Otherwise the VSYS regulator
current drains the battery when left unused for long period. After the
UVLO there is only reference block in the Phaser drawing current from
the battery. The UVLO has a little hysteresis and is cancelled when the
battery voltage has risen to 2.7V. However, reset to the CPU is given only
when battery voltage rises to 3.45V. This in order to avoid unsuccessful
power–ups. When the lockout voltage level is reached, the battery volt-
age rises because the load is removed.
PDA CPU
The PDA CPU is a SC450–33CC in a 256 pin plastic ball grid array pack-
age.
age.
The core features a 32–bit architecture with internal 8k write–back cache.
The clock rate is 33MHz, which can be slowed down to1MHz. The de-
fault clock rate on reset is 8.29MHz. The bus clock rate is 33MHz. A
32kHz clock signal for the BS8 module is provided by the CPU PLL cir-
cuit. The clock signal is started when ever the system voltage is applied
to the CPU.
The clock rate is 33MHz, which can be slowed down to1MHz. The de-
fault clock rate on reset is 8.29MHz. The bus clock rate is 33MHz. A
32kHz clock signal for the BS8 module is provided by the CPU PLL cir-
cuit. The clock signal is started when ever the system voltage is applied
to the CPU.
The CORE starts when the reset signal is provided and then it begins to
execute the program code from the Flash memory. The external pull–up
resistor controls the start–up procedure (Boot code Chip select, and data
bus width).
execute the program code from the Flash memory. The external pull–up
resistor controls the start–up procedure (Boot code Chip select, and data
bus width).