Intel i5-2500 BX80623I52500 User Manual
Product codes
BX80623I52500
Datasheet, Volume 1
17
Introduction
PEG
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
Processor
The 64-bit, single-core or multi-core component (package).
Processor Core
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Processor Graphics
Intel
®
Processor Graphics
Rank
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SO-
DIMM.
SCI
System Control Interrupt. Used in ACPI protocol.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
TAC
Thermal Averaging Constant.
TDP
Thermal Design Power.
V
AXG
Graphics core power supply.
V
CC
Processor core power supply.
V
CCIO
High Frequency I/O logic power supply
V
CCPLL
PLL power supply
V
CCSA
System Agent (memory controller, DMI, PCIe controllers, and display engine)
power supply
V
DDQ
DDR3 power supply.
VLD
Variable Length Decoding.
V
SS
Processor ground.
x1
Refers to a Link or Port with one Physical Lane.
x16
Refers to a Link or Port with sixteen Physical Lanes.
x4
Refers to a Link or Port with four Physical Lanes.
x8
Refers to a Link or Port with eight Physical Lanes.
Term
Description