Panasonic PT-50LC13 User Manual

Page of 46
PT-50LC13
VIDEO SIGNAL PATH II BLOCK DIAGRAM (1/2)
LCD DRIVE C.B.A.
P2501-14
P2501-15
P2501-11
P2501-12
P2501-8
P2501-9
P2501-2
P2501-3
P2501-5
P2501-6
IC2008 (LEVEL SHIFTER)
IC2505 (COLOR CORRECTION/LCD TIMING GENERATOR)
IC2502 (LVDS RECEIVER)
IC2504
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
0/5V ---> 0/15.3V
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
LEVEL SHIFTER
11
5
9
6
10
8
7
26
24
20
27
23
19
22
28
18
Q2010, 2011
LEVEL SHIFTER
Q2009
Q2001, 2002
Q2003, 2004
Q2005, 2006
Q2007, 2008
VCC
1,30
VCC
+5V
2
1,12,26,35,44,56,66,
75,80,88,89,98,109,
131,132,155,176
19,20,24,25,
27-30,32,33
160-162,
164-168 
147-154
136-141,
143,144 
30,32-35,
37-39
41-43,45-47,
49,50
1-3,5,51,
53-55
50,51,53-55,
58-62
82,83,85-87,
90-92,94,95
VCC
+3.3V
+5V
+2.5V
REG.
VCC
38
37
36
34
40
70
69
67
63
100
99
68
97
96
114
71
72
76
77
115
78
116
79
10
9
12
11
16
15
20
19
18
17
7
8
13
6
29
27
26
120
119
121
122
1
8
15,45,74,103,133,163
IC2501
+3.3V
REG.
VCC
4
5
13,23,31,40,48,56
<FROM IC2304(60)> XDIR X
<FROM IC2304(59)> DIR X
<FROM IC2304(50)> DIR Y
DY
DX
CLY
CLX
ENABLE 4
ENABLE 3
ENABLE 2
ENABLE 1
NRG
H-SYNC
V-SYNC
H-SYNC
R DATA (8BIT)
LVDS DATA A(+)
FROM VIDEO I 
SIGNAL PATH 
BLOCK DIAGRAM
LVDS DATA A(-)
LVDS DATA B(+)
LVDS DATA B(-)
LVDS DATA C(+)
LVDS DATA C(-)
LVDS DATA D(+)
LVDS DATA D(-)
LVDS CLOCK(+)
LVDS CLOCK(-)
G DATA (8BIT)
B DATA (8BIT)
R DATA (10BIT)
G DATA (10BIT)
B DATA (10BIT)
V-SYNC
CLOCK(76 MHz)
SERIAL CLOCK
SERIAL DATA 1
CS(L)
SERIAL CLOCK
FROM
SYSTEM CONTROL
BLOCK DIAGRAM
SERIAL DATA 1
CS(L)
<FROM IC2304(52)> RESET(L)
<FROM IC2304(57)> CORRECT ON(L)
RESET(L)
CORRECT ON(L)
FRP
XFRP
STSQE(R)
STSQO(R)
XFR(R)
S/H CLOCK(R)
STSQE(G)
STSQO(G)
XFR(G)
S/H CLOCK(G)
STSQE(B)
STSQO(B)
XFR(B)
S/H CLOCK(B)
LVDS SERIAL TO
TTL PARALLEL
CONVERTER
PLL
+15.3V
VIDEO SIGNAL PATH II BLOCK DIAGRAM (1/2)