Intel Mobile Intel Celeron RH80532NC049256 Data Sheet

Datasheet

23

The BSEL[2:0] signals are used to select the frequency of the processor input clock 

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate 

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in 

.

The FSB signals have been combined into groups by buffer type in the following 

sections. AGTL+ input signals have differential input buffers, which use GTLREF as a 

reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input 

group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers 

to the AGTL+ output group as well as the AGTL+ I/O group when driving. 

With the implementation of a source synchronous data bus, two sets of timing 

parameters need to be specified. One set is for common clock signals, which are 

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second 

set is for the source synchronous signals, which are relative to their respective strobe 

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are 

still present (A20M#, IGNNE#, etc.) and can become active at any time during the 

clock cycle. 

 identifies which signals are common clock, source synchronous, 

and asynchronous.

L

L

L

RESERVED

L

L

H

133 MHz

L

H

H

RESERVED

L

H

L

200 MHz

H

H

L

RESERVED

H

H

H

RESERVED

H

L

H

RESERVED

H

L

L

RESERVED