Intel i5-2500K BX80623I52500K User Manual

Datasheet, Volume 1

23

Interfaces

Command Overlap allows the insertion of the DRAM commands between the Activate, 
Precharge, and Read/Write commands normally used, as long as the inserted 
commands do not affect the currently executing command. Multiple commands can be 
issued in an overlapping manner, increasing the efficiency of system memory protocol.

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, 
the IMC continuously monitors pending requests to system memory for the best use of 
bandwidth and reduction of latency. If there are multiple requests to the same open 
page, these requests would be launched in a back to back manner to make optimum 
use of the open memory page. This ability to reorder requests on the fly allows the IMC 
to further reduce latency and increase bandwidth efficiency.

The processor has 2 additional MTRRs (total 10 MTRRs). These additional MTRRs are 
specially important in supporting larger system memory beyond 4 GB.

The memory controller incorporates a DDR3 Data Scrambling feature to minimize the 
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the 
data bus. Past experience has demonstrated that traffic on the data bus is not random 
and can have energy concentrated at specific spectral harmonics creating high di/dt 
that is generally limited by data patterns that excite resonance between the package 
inductance and on-die capacitances. As a result, the memory controller uses a data 
scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce 
the impact of any excessive di/dt.