Intel i5-2500K BX80623I52500K User Manual

Datasheet, Volume 1

51

Power Management

No additional power reduction actions are taken in the package C1 state. However, if 
the C1E sub-state is enabled, the processor automatically transitions to the lowest 
supported core clock frequency, followed by a reduction in voltage.

The package enters the C1 low power state when:

• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.

The package enters the C1E state when:

• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is 

limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.

• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is 

enabled in IA32_MISC_ENABLES.

No notification to the system occurs upon entry to C1/C1E.

A processor enters the package C3 low power state when:

• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been 

granted permission by the platform. 

• The platform has not granted a request to a package C6 state but has allowed a 

package C6 state.

In package C3-state, the L3 shared cache is valid.

A processor enters the package C6 low power state when:

• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been 

granted permission by the platform.

In package C6 state, all cores have saved their architectural state and have had their 
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable 
in this state. The processor remains in package C6 state as long as any part of the L3 
cache is active.