Intel i5-2500K BX80623I52500K User Manual

Intel

Product codes

BX80623I52500K

Datasheet, Volume 1

7

Tables

1-1 PCIe Supported Configurations in Desktop Products..................................................... 12
1-2 Related Documents ................................................................................................. 18
2-1 Supported UDIMM Module Configurations ................................................................... 19
2-2 Supported SO-DIMM Module Configurations (AIO Only)................................................ 20
2-3 DDR3 System Memory Timing Support ...................................................................... 20
2-4 Reference Clock...................................................................................................... 33
4-1 System States........................................................................................................ 43
4-2 Processor Core/Package State Support ...................................................................... 43
4-3 Integrated Memory Controller States ......................................................................... 44
4-4 PCIe Link States ..................................................................................................... 44
4-5 DMI States ............................................................................................................ 44
4-6 Processor Graphics Controller States ......................................................................... 44
4-7 G, S and C State Combinations ................................................................................. 45
4-8 Coordination of Thread Power States at the Core Level ................................................ 47
4-9 P_LVLx to MWAIT Conversion ................................................................................... 47
4-10 Coordination of Core Power States at the Package Level............................................... 50
6-1 Signal Description Buffer Types ................................................................................ 59
6-2 Memory Channel A.................................................................................................. 60
6-3 Memory Channel B.................................................................................................. 61
6-4 Memory Reference and Compensation ....................................................................... 61
6-5 Reset and Miscellaneous Signals ............................................................................... 62
6-6 PCI Express* Graphics Interface Signals .................................................................... 63
6-7 Intel

Flexible Display Interface ............................................................................... 63

6-8 DMI - Processor to PCH Serial Interface ..................................................................... 64
6-9 PLL Signals ............................................................................................................ 64
6-10 TAP Signals............................................................................................................ 64
6-11 Error and Thermal Protection.................................................................................... 65
6-12 Power Sequencing .................................................................................................. 65
6-13 Processor Power Signals .......................................................................................... 66
6-14 Sense Pins ............................................................................................................. 66
6-15 Ground and NCTF ................................................................................................... 66
6-16 Processor Internal Pull Up/Pull Down ......................................................................... 67
7-1 VR 12.0 Voltage Identification Definition .................................................................... 71
7-2 VCCSA_VID configuration ........................................................................................ 74
7-3 Signal Groups 1...................................................................................................... 75
7-4 Storage Condition Ratings........................................................................................ 77
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 78
7-6 Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications ........... 80
7-7 Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications ....... 81
7-8 DDR3 Signal Group DC Specifications ........................................................................ 81
7-9 Control Sideband and TAP Signal Group DC Specifications ............................................ 82
7-10 PCIe DC Specifications............................................................................................. 83
7-11 PECI DC Electrical Limits.......................................................................................... 85
8-1 Processor Pin List by Pin Name ................................................................................. 92
9-1 DDR Data Swizzling Table – Channel A .................................................................... 108
9-2 DDR Data Swizzling Table – Channle B .................................................................... 109