Samsung M471B5273BH1-CF8 Leaflet
M471B5273BH1-CF700/CF800/CH900/CK000
Organization : 512M x 64
Composition : 256M x 8 * 16ea
Used component part # : K4B2G0846B-HCF7/CF8/CH9/CK0
# of rows in module : 2 Rows
# of banks in component : 8 Banks
Feature : 30mm height & double sided component
Refresh : 8K/64ms
Bin Sort : F7(DDR3 800@CL=6), F8(DDR3 1066@CL=7), H9(DDR3 1333@CL=9), K0(DDR3 1600@CL=11)
Composition : 256M x 8 * 16ea
Used component part # : K4B2G0846B-HCF7/CF8/CH9/CK0
# of rows in module : 2 Rows
# of banks in component : 8 Banks
Feature : 30mm height & double sided component
Refresh : 8K/64ms
Bin Sort : F7(DDR3 800@CL=6), F8(DDR3 1066@CL=7), H9(DDR3 1333@CL=9), K0(DDR3 1600@CL=11)
Byte
#
Function Described
Function Supported
Hex Value
Note
CF700
CF800
CH900
CF700 CF800 CH900
0
Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage
CRC coverage 0~116Byte, SPD Byte
Total :256Byte, SPD Byte Use :
176Byte
92h
1
SPD Revision
Version 1.0
10h
2
Key Byte / DRAM Device Type
DDR3 SDRAM
0Bh
3
Key Byte / Module Type
Unbuffered SoDIMM
03h
4
SDRAM Density and Banks
2Gb 8banks
03h
5
SDRAM Addressing
Row : 15, Column : 10
19h
6
Module Nominal Voltage, VDD
1.5V only
00h
7
Module Organization
2Rank / x8
09h
8
Module Memory Bus Width
Non ECC, 64bit
03h
9
Fine Timebase Dividend and Divisor
2.5ps
52h
10
Medium Timebase Dividend
1/8 (0.125ns)
01h
11
Medium Timebase Divisor
1/8 (0.125ns)
08h
12
SDRAM Minimum Cycle Time (tCKmin)
2.5ns
1.875ns
1.5ns
14h
0Fh
0Ch
13
Reserved
Reserved
00h
14
CAS Latencies Supported, Least Significant Byte
6
6, 7, 8
6, 7, 8, 9
04h
1Ch
3Ch
15
CAS Latencies Supported, Most Significant Byte
6
6, 7, 8
6, 7, 8, 9
00h
16
Minimum CAS Latency Time(tAAmin)
15ns
13.125ns
13.125ns
78h
69h
69h
17
Minimum Write Recovery Time (tWRmin)
15ns
78h
18
Minimum RAS# to CAS# Delay Time (tRCDmin)
15ns
13.125ns
13.125ns
78h
69h
69h
19
Minimum Row Active to Row Active Delay Time (tRRDmin)
10ns
7.5ns
6ns
50h
3Ch
30h
20
Minimum Row Precharge Delay Time (tRPmin)
15ns
13.125ns
13.125ns
78h
69h
69h
21
Upper Nibbles for tRAS and tRC
-
11h
22
Minimum Active to Precharge Time (tRASmin), Least Significant Byte
37.5ns
37.5ns
36ns
2Ch
2Ch
20h
23
Minimum Active to Active/Refresh Time (tRCmin), Least Significatn Byte
52.5ns
50.625ns
49.125ns
A4h
95h
89h
24
Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte
160ns
00h
25
Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte
160ns
05h
26
Minimum Internal Write to Read Command Delay Time (tWTRmin)
7.5ns
3Ch
27
Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
7.5ns
3Ch
28
Upper Nibble for tFAW
40ns
37.5ns
30ns
01h
01h
00h
29
Minimum Four Activate WIndow Delay Time (tFAWmin), Least Significant Byte
40ns
37.5ns
30ns
40h
2Ch
F0h
30
SDRAM Optional Features
DLL off Mode, RZQ/6, RZQ/7
83h
31
SDRAM Thermal and Refresh Options
No ODTS, No ASR
01h
32
Module Thermal Sensor
without TS
00h
33
SDRAM Device Type
Standard Monolithic DRAM Device
00h
34~59
Reserved, General Section
-
00h
60
Module Nominal Height
30mm
0Fh
61
Module Maximum Thickness
Planar Double sides
11h
62
Reference Raw Card Used
R/C F, 2.0
45h
63
Address Mapping from Edge Connector to DRAM
standard
00h
SERIAL PRESENCE DETECT
MAY. 2009