Epson 6200A User Manual
10
EPSON
S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
2.3 ALU (Arithmetic Logic Unit) and Registers
Table 2.3.1 shows ALU operations between the 4-bit registers, TEMPA and TEMPB.
Table 2.3.1 ALU register operation
Add, without carry
Add, with carry
Subtract, without borrow
Subtract, with borrow
Logical-AND
Logical-OR
Exclusive-OR
Comparison
Flag bit test
Rotate right, with carry
Rotate left, with carry
Invert
Operation
Instruction
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
FAN
RRC
RLC
NOT
The Z (zero) flag is set when the result of ALU operation is
C
3
2
1
0
X
0
0
0
0
X
: Don't care.
The C (carry) flag is set when an add operation causes a carry or when a subtract operation causes a
borrow.
borrow.
2.3.1 D (decimal) flag and decimal operations
Setting the D (decimal) flag activates the decimal mode, allowing decimal addition and subtraction. Table
2.3.1.1 shows the relations of actual (decimal) results, ALU outputs, and the values of the C and Z flags.
2.3.1.1 shows the relations of actual (decimal) results, ALU outputs, and the values of the C and Z flags.
Table 2.3.1.1 Results of hexadecimal and decimal operations
Subtraction
Addition
Actual
result
D = 0 : Result of
hexadecimal operation
ALU output
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
D
E
F
Z
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D = 1 : Result of
decimal operation
ALU output
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
D
E
F
0
1
2
3
4
5
1
2
3
4
5
Z
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
C
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Actual
result
D = 0 : Result of
hexadecimal operation
ALU output
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
D
E
F
Z
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-16
-15
-14
-13
-12
-11
-10
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
11
12
13
14
15
D = 1 : Result of
decimal operation
ALU output
A
B
C
D
E
F
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
D
E
F
Z
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0