Intel Mobile Intel Pentium 4 RH80532GC021512 User Manual

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3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source 

synchronous data signals are referenced to the falling edge of their associated data strobe. Source 
synchronous address signals are referenced to the rising and falling edge of their associated address strobe. 
All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.

4. Unless otherwise noted these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF 

at 2/3 V

CC

 

± 2%.

6. Specification is for a minimum swing defined between AGTL+ V

IL_MAX

 to V

IH_MIN

. This assumes an edge rate 

of 0.3 V/ns to 4.0V/ns.

7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each 

respective strobe.

8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the 

 850 Chipset Platform Design Guide for more information on the 

definitions and use of these specifications.

9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the 

 850 Chipset Platform Design Guide for more information on the 

definitions and use of these specifications.

10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of 

ADSTB#.

11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.

12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after 

the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 
BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must 
come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#.

13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All 

Asynch GTL+ signal timings are referenced at GTLREF.

3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the 

assertion and before the deassertion of  PROCHOT# for the processor to complete current instruction 
execution.

6. See section Section 7.2 for additional timing requirements for entering and leaving the low power states.

1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
3. After the assertion of RESET#.

T35: Asynch GTL+ Input Pulse Width, except 

PWRGOOD

2

BCLKs

T36: PWRGOOD to RESET# de-assertion 

time

1

10

ms

T37: PWRGOOD Inactive Pulse Width

10

BCLKs

4

T38: PROCHOT# pulse width

500

us

5

T45:  Reset Configuration Signals (A[31:3]#, 

BR0#, INIT#, SMI#) Setup Time

4

BCLKs

1

T46: Reset Configuration Signals (A[31:3]#, 

BR0#, INIT#, SMI#) Hold Time

2

20

BCLKs

2