SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

181

Revision 1.4 (08-19-08)

 

This section details the Host MAC and TX/RX FIFO related System CSR’s. 

These Host Bus Interface accessible registers allow for the configuration of the TX/RX FIFO’s, Host
MAC and indirect access to the complete set of Host MAC CSR’s. The Host MAC CSR’s are
accessible through the Host Bus Interface via the 

 and 

For more information on the TX/RX FIFO’s, refer to 

.

The full list of Host MAC CSR’s are described in 

. For more information on the Host MAC, refer to 

.

This register controls the Host MAC receive engine.

Offset:

06Ch

Size:

32 bits

31:30

RX End Alignment (RX_EA)
This field specifies the alignment that must be maintained on the last data 
transfer of a buffer. The LAN9311/LAN9311i will add extra DWORD’s of 
data up to the alignment specified in the table below. The host is 
responsible for removing these extra DWORD’s. This mechanism can be 
used to maintain cache line alignment on host processors.

The desired RX End Alignment must be set before reading a 
packet. The RX End Alignment can be changed between reading 
receive packets, but must not be changed if the packet is partially 
read.

R/W

00b

29:28

RO

-

27:16

RX DMA Count (RX_DMA_CNT)
This 12-bit field indicates the amount of data, in DWORD’s, to be 
transferred out of the RX Data FIFO before asserting the 

. After being set, this field is decremented for each DWORD of 

data that is read from the RX Data FIFO. This field can be overwritten with 
a new value before it reaches zero.

R/W

000h

15

Force RX Discard (RX_DUMP)
When a 1 is written to this bit, the RX Data and Status FIFO’s are cleared 
of all pending data and the RX data and status pointers are cleared to zero.

Please refer to 

 for a detailed description regarding the use 

of RX_DUMP.

WO

SC

0b