SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

234

SMSC LAN9311/LAN9311i

 

This read/write register allows for the manual configuration of the switch Port 0(Host MAC) flow control.
This register also provides read back of the currently enabled flow control settings, whether set
manually or Auto-Negotiated. Refer to 

 for

additional information.

The flow control values in the 

 are not affected by the values of this register.

Offset:

1A8h

Size:

32 bits

31:8

RO

-

7

Port 0 Hard-wired Flow Control (HW_FC_MII)
When set to “1”, the Host MACs RX FIFO level is connected to the switch 
engine’s transmitter and the switch engines RX FIFO level is connected to 
the Host MACs transmitter. This achieves lower latency flow control.

All other flow control methods must be disabled when using this 
feature. (MANUAL_FC_MII should be set, TX_FC_MII, 
RX_FC_MII, and BP_EN_MII should be cleared. FCANY, FCADD, 
FCBRD, and FCMULT in the AFC_CFG register should be 
cleared).

R/W

0b

6

Port 0 Backpressure Enable (BP_EN_MII)
This bit enables/disables the generation of half-duplex backpressure on 
switch Port 0.

R/W

5

Port 0 Current Duplex (CUR_DUP_MII)
This bit indicates the actual duplex setting of the switch Port 0.

RO

4

Port 0 Current Receive Flow Control Enable (CUR_RX_FC_MII)
This bit indicates the actual receive flow setting of switch Port 0

RO

3

Port 0 Current Transmit Flow Control Enable (CUR_TX_FC_MII)
This bit indicates the actual transmit flow setting of switch Port 0.

RO

2

Port 0 Receive Flow Control Enable (RX_FC_MII)
When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is 
disabled, this bit enables/disables the detection of full-duplex Pause packets 
on switch Port 0.

R/W