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SMSC LAN9311 User Manual

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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
307
Revision 1.4 (08-19-08)
DATASHEET
 
14.4.2.12
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the 
.
Index (decimal):
30
Size:
16 bits
BITS
DESCRIPTION
TYPE
DEFAULT
15:8
RESERVED
RO
-
7
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
6
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
5
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
4
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated) 
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
3
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge 
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
2
INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
1
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received 
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
R/W
0b
0
RESERVED
RO
-