SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

323

Revision 1.4 (08-19-08)

 

This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates
an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related
interrupts in this register may be masked via the 

register. When an unmasked switch fabric interrupt is generated in this register, the interrupt will trigger
the SWITCH_INT bit in the 

. Refer to 

 for more information.

Register #:

0005h

Size:

32 bits

31:7

RO

-

6

Buffer Manager Interrupt (BM)
Set when any unmasked bit in the 

 is triggered. This bit is cleared upon a read.

RC

0b

5

Switch Engine Interrupt (SWE)
Set when any unmasked bit in the 

 is triggered. This bit is cleared upon a read.

RC

0b

4:3

RO

-

2

Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see 

) is triggered. This bit is cleared upon a read.

RC

0b

1

Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see 

) is triggered. This bit is cleared upon a read.

RC

0b

0

Port 0 MAC Interrupt (MAC_MII)
Set when any unmasked bit in the MAC_IPR_MII register (see 

) is triggered. This bit is cleared upon a read.

RC

0b