SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

368

SMSC LAN9311/LAN9311i

 

This section details the switch engine related CSRs. These registers allow configuration and monitoring
of the various switch engine components including the ALR, VLAN, Port VID, and DIFFSERV tables.
A list of the general switch CSRs and their corresponding register numbers is included in 

.

This register is used to manually read and write MAC addresses from/into the ALR table. 

 and 

 should be read following the setting of bit

1(Get First Entry) or bit 0(Get Next Entry) of this register.

For write access, the 

 and 

 registers should first be written with the

MAC address, followed by the setting of bit 2(Make Entry) of this register. The Make Pending bit in the

 register indicates when the

command is finished.

Refer to 

 for more information.

Register #:

1800h

Size:

32 bits

31:3

RO

-

2

Make Entry
When set, the contents of ALR_WR_DAT_0 and ALR_WR_DAT_1 are 
written into the ALR table. The ALR logic determines the location where the 
entry is written. This command can also be used to change or delete a 
previously written or automatically learned entry. This bit has no affect when 
written low. This bit must be cleared once the ALR Make command is 
completed, which can be determined by the ALR Status bit in the 

 register.

R/W

0b

1

Get First Entry
When set, the ALR read pointer is reset to the beginning of the ALR table 
and the ALR table is searched for the first valid entry, which is loaded into 
the ALR_RD_DAT_0 and ALR_RD_DAT_1 registers. The bit has no affect 
when written low. This bit must be cleared after it is set.

R/W

0b

0

Get Next Entry
When set, the next valid entry in the ALR MAC address table is loaded into 
the ALR_RD_DAT_0 and ALR_RD_DAT_1 registers. This bit has no affect 
when written low. This bit must be cleared after it is set.

R/W

0b