SMSC LAN9311 User Manual
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08)
410
SMSC LAN9311/LAN9311i
DATASHEET
14.5.3.39
Switch Engine Interrupt Mask Register (SWE_IMR)
This register contains the Switch Engine interrupt mask, which masks the interrupts in the
. All Switch Engine interrupts are masked by setting the
Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to
for more information.
Register #:
1880h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:1
RESERVED
RO
-
0
Interrupt Mask
When set, this bit masks interrupts from the Switch Engine. The status bits
in the
When set, this bit masks interrupts from the Switch Engine. The status bits
in the
are not
affected.
R/W
1b