Sun Microsystems enterprise server 220r User Manual
Chapter 4
Hardware Configuration
67
About CPU Modules
The UltraSPARC II CPU module is a high-performance, highly-integrated
superscalar processor implementing the SPARC-V9 64-bit reduced instruction set
computer (RISC) architecture. The UltraSPARC II processor supports both 2-D and
3-D graphics, as well as image processing, video compression and decompression,
and video effects through the sophisticated visual instruction set (VIS). VIS provides
high levels of multimedia performance, including real-time video compression/
decompression and two streams of MPEG-2 decompression at full broadcast quality
with no additional hardware support.
superscalar processor implementing the SPARC-V9 64-bit reduced instruction set
computer (RISC) architecture. The UltraSPARC II processor supports both 2-D and
3-D graphics, as well as image processing, video compression and decompression,
and video effects through the sophisticated visual instruction set (VIS). VIS provides
high levels of multimedia performance, including real-time video compression/
decompression and two streams of MPEG-2 decompression at full broadcast quality
with no additional hardware support.
The system’s main logic board provides slots for two UltraSPARC II CPU modules.
Each processor module includes one CPU chip with integrated cache memory for
data and instructions, as well as 1 Mbyte or more of external static random access
memory (SRAM) cache memory.
Each processor module includes one CPU chip with integrated cache memory for
data and instructions, as well as 1 Mbyte or more of external static random access
memory (SRAM) cache memory.
Processor modules communicate with the system’s main memory and I/O
subsystem via the system’s high-speed Ultra Port Architecture (UPA) data bus.
The UPA’s clock rate is automatically synchronized with the clock speed of the CPU
modules. The UPA’s clock rate operates at a ratio of the CPU’s clock speed. For
example, if the CPUs operate at 450 MHz, the UPA data bus could operate at one
fourth the clock speed at 112.5 MHz.
subsystem via the system’s high-speed Ultra Port Architecture (UPA) data bus.
The UPA’s clock rate is automatically synchronized with the clock speed of the CPU
modules. The UPA’s clock rate operates at a ratio of the CPU’s clock speed. For
example, if the CPUs operate at 450 MHz, the UPA data bus could operate at one
fourth the clock speed at 112.5 MHz.
A qualified service provider must remove and replace CPU modules in your system.
For information about installing and removing CPU modules, see the Sun Enterprise
220R Server Service Manual.
For information about installing and removing CPU modules, see the Sun Enterprise
220R Server Service Manual.
Configuration Rules
The following rules apply for your system:
■
You can install one or two UltraSPARC II CPU modules into the server.
■
The first CPU module must be installed in the slot labeled CPU0—the one closest
to the system’s four PCI slots.
to the system’s four PCI slots.
■
If you install more than one CPU module, the modules must operate at identical
clock speeds (450 MHz, for example) and they must have the same size cache
memory. This generally means the CPU modules must have the same part
number.
clock speeds (450 MHz, for example) and they must have the same size cache
memory. This generally means the CPU modules must have the same part
number.
For information about the CPU slot locations on the main logic board, see the Sun
Enterprise 220R Server Service Manual.
Enterprise 220R Server Service Manual.