SMSC SCH5617 User Manual

SMSC SCH5617

Revision 0.6 (01-09-08) 

 

„

ACPI 2.0 Compliant

„

High Performance 8051

— 2.5X average instruction execution speed improvement 

over the entire instruction set; i.e., typical 4-clock 
instruction cycle in high-performance 8051 vs. 12-clock 
instruction cycle in standard 8051.

— Faster clock speed: 32 MHz vs. 16 MHz in standard 

8051. 

— Dual Data Pointers
— More Interrupts: Power-Fail, External Interrupt 2, 

External Interrupt 3, etc.

— A set of External Memory/Mapped Control Registers 

provides the 80C51 core with the ability to directly 
control many functional blocks of the SCH5617.

— 384 Bytes of RAM as part of the 8051 core
— 4k Bytes Data RAM (869 bytes may be used to patch 

ROM code)

— Twelve Interrupt Sources
— Watch Dog Timer (WDT)

„

PECI Interface

„

Temperature Monitor

— Monitoring of up to Two Remote Thermal Diodes
— Supports temperature readings from -63 degrees to 

+192 degrees

– Supports monitoring of discrete diodes (3904 type 

diodes)

– Supports monitoring substrate diodes (45nm & 

65nm processor diodes)

— 1/8th degree temperature resolution
— Internal Ambient Temperature Measurement
— Limit Comparison of all Monitored Values

„

PROCHOT_IN# Pin

— Mapped into Temperature monitoring interrupt 

generation logic

— May be used to adjust fan control limits
— May be configured to force fans on full

„

PROCHOT_OUT Pin

„

Auto-Fan Control with ProcHot Features

— PWM (Pulse width Modulation) Outputs (3) 

– Legacy PWM control dc fan outputs

— High Frequency PWM Options (15kHz up to 30kHz)
— 2 second delayed start-up for PWM outputs
— Fan Tachometer or Lock Rotor Inputs (3)
— Programmable linear automatic fan control based on 

temperature

— Acoustic enhancement mode
— ProcHot pins modulate Tmin
— Fan PWM duty cycle is a function in linear mode of 

multiple temperatures and ProcHot signals

— PWM Ramp Rate Closed Loop Control

„

Internal Ring Oscillator for VTR Powered Logic

„

Low Battery Warning

„

LED Control

„

SMBus Isolation Logic

„

Programmable Wake-up Event Interface

„

PC2001 Compliant

„

General Purpose Input/Output Pins (30 Host 

controlled, 16 8051 controlled)

„

21 Dedicated Scratchpad registers

„

ISA Plug-and-Play Compatible Register Set

„

System Management Interrupt

„

GLUE Logic

— IDE Reset/Buffered PCI Reset Outputs
— Power OK Signal Generation
— Power Sequencing
— Power Supply Turn On Circuitry
— Resume Reset Signal Generation
— Hard Drive Front Panel LED

„

2.88MB Super I/O Floppy Disk Controller

— Licensed CMOS 765B Floppy Disk Controller
— Software and Register Compatible with SMSC's 

Proprietary 82077AA Compatible Core

— Supports Two Floppy Drives
— Configurable Open Drain/Push-Pull Output Drivers
— Supports Vertical Recording Format
— 16-Byte Data FIFO
— 100% IBM® Compatibility
— Detects All Overrun and Underrun Conditions
— Sophisticated Power Control Circuitry (PCC) Including 

Multiple Powerdown Modes for Reduced Power 
Consumption

— DMA Enable Logic
— Data Rate and Drive Control Registers
— 480 Addresses, Up to Eight IRQs, and Four DMA 

Options

— Enhanced Digital Data Separator

– 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps 

Data Rates

– Programmable Pre compensation Modes