Intel i3-2100 BX80623I32100 User Manual

Product codes

BX80623I32100

Datasheet, Volume 1

4.2.5.1

Package C0 .............................................................................. 51

4.2.5.2

Package C1/C1E ....................................................................... 51

4.2.5.3

Package C3 State...................................................................... 52

4.2.5.4

Package C6 State...................................................................... 52

4.3

Integrated Memory Controller (IMC) Power Management ........................................ 52
4.3.1

Disabling Unused System Memory Outputs ................................................ 52

4.3.2

DRAM Power Management and Initialization ............................................... 53
4.3.2.1

Initialization Role of CKE ............................................................ 54

4.3.2.2

Conditional Self-Refresh............................................................. 54

4.3.2.3

Dynamic Power-down Operation ................................................. 55

4.3.2.4

DRAM I/O Power Management .................................................... 55

4.4

PCI Express* Power Management ........................................................................ 55

4.5

Direct Media Interface (DMI) Power Management .................................................. 55

4.6

Graphics Power Management .............................................................................. 56
4.6.1

Intel

Rapid Memory Power Management (Intel

RMPM)

(also known as CxSR) ............................................................................. 56

4.6.2

Intel

Graphics Performance Modulation Technology (Intel

GPMT) .............. 56

4.6.3

Graphics Render C-State ......................................................................... 56

4.6.4

Intel

Smart 2D Display Technology (Intel

S2DDT) .................................. 56

4.6.5

Intel

Graphics Dynamic Frequency.......................................................... 57

4.7

Thermal Power Management ............................................................................... 57

Thermal Management .............................................................................................. 59

Signal Description ................................................................................................... 61
6.1

System Memory Interface Signals........................................................................ 62

6.2

Memory Reference and Compensation Signals ....................................................... 63

6.3

Reset and Miscellaneous Signals.......................................................................... 64

6.4

PCI Express*-Based Interface Signals .................................................................. 65

6.5

Intel

Flexible Display Interface (Intel

FDI) Signals ............................................. 65

6.6

Direct Media Interface (DMI) Signals.................................................................... 66

6.7

Phase Lock Loop (PLL) Signals ............................................................................ 66

6.8

Test Access Points (TAP) Signals ......................................................................... 66

6.9

Error and Thermal Protection Signals ................................................................... 67

Electrical Specifications ........................................................................................... 71
7.1

Power and Ground Lands.................................................................................... 71

7.2

Decoupling Guidelines ........................................................................................ 71
7.2.1

Voltage Rail Decoupling........................................................................... 71

7.3

Processor Clocking (BCLK[0], BCLK#[0]) .............................................................. 72
7.3.1

Phase Lock Loop (PLL) Power Supply......................................................... 72

7.4

Voltage Identification (VID) .......................................................................... 72

7.5

System Agent (SA) VCC VID ............................................................................... 76

7.6

Reserved or Unused Signals................................................................................ 76

7.7

Signal Groups ................................................................................................... 77

7.8

Test Access Port (TAP) Connection....................................................................... 78

7.9

Storage Conditions Specifications ........................................................................ 79

7.10 DC Specifications .............................................................................................. 80

7.10.1 Voltage and Current Specifications............................................................ 80

7.11 Platform Environmental Control Interface (PECI) DC Specifications........................... 86

7.11.1 PECI Bus Architecture ............................................................................. 86
7.11.2 DC Characteristics .................................................................................. 87