Intel Pentium 4 672 HH80547PG1122MH User Manual

                                               

   

17

 

1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals do not have on-die termination and must be terminated on the system board.
3. In processor systems where there is no debug port implemented on the system board, these signals are used 

to support a debug port interposer. In systems with the debug port implemented on the system board, these 
signals are no connects.

4. These signal groups are not terminated by the processor. Refer to section 2.5 and the Intel® Pentium® 4 

Processor and Intel® 850 Chipset Platform Design Guide and ITP700 Debug Port Design Guide for 
termination requirements and further details.

5. The value of these pins during the active-to-inactive edge of RESET# determine processor configuration 

options. See Section 7.1 for details.

 

Pentium 4 processors do not utilize CMOS voltage levels on any signals that connect to the 
processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, 
LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output 
FERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize GTL+ output 
buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the 
outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major 
difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications 
in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be 
asserted for at least two BCLKs in order for the processor to recognize them. See Section 2.10 and 
Section 2.12 for the DC and AC specifications for the Asynchronous GTL+ signal groups. See 
section Section 7.2 for additional timing requirements for entering and leaving the low power 
states.

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is 
recommended that the Pentium 4 processor be first in the TAP chain and followed by any other 
components within the system. A translation buffer should be used to connect to the rest of the 
chain unless one of the other components is capable of accepting an input of the appropriate 

AGTL+ Strobes

Synchronous 
to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Asynchronous GTL+ Input

4

A20M#, DBR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, 
PWRGOOD, SMI#, SLP#, STPCLK#

Asynchronous GTL+ Output

4

FERR#, IERR#, THERMTRIP#, PROCHOT#

TAP Input

4

Synchronous 
to TCK

TCK, TDI, TMS, TRST#

TAP Output

4

Synchronous 
to TCK

DBR

3

, TDO

System Bus Clock

Clock

BCLK[1:0], ITP_CLK[1:0]

3

Power/Other

V

CC

, V

CCA

, V

CCIOPLL

, VID[4:0], V

SS

, V

SSA

, GTLREF[3:0], 

COMP[1:0], RESERVED, SKTOCC#, TESTHI[10:0], 
THERMDA, THERMDC, V

CC_SENSE

, V

SS_SENSE