Intel Pentium 4 672 HH80547PG1122MH User Manual
Product codes
HH80547PG1122MH
Intel
®
Pentium
®
4 Processor in the 423-pin Package
32
3.2
System Bus Signal Quality Specifications and
Measurement Guidelines
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the Intel
available in the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide.
Table 17 provides the signal quality specifications for all processor signals for use in simulating
signal quality at the processor silicon. Signal quality measurements cannot be made at the
processor pins.
signal quality at the processor silicon. Signal quality measurements cannot be made at the
processor pins.
The Pentium 4 processor maximum allowable overshoot and undershoot specifications for a given
duration of time are detailed in Table 18 through Table 21. Figure 13 shows the system bus
ringback tolerance for low-to-high transitions and Figure 14 shows ringback tolerance for high-to-
low transitions.
duration of time are detailed in Table 18 through Table 21. Figure 13 shows the system bus
ringback tolerance for low-to-high transitions and Figure 14 shows ringback tolerance for high-to-
low transitions.
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all Pentium 4 processor frequencies.
3. Specifications are for the edge rate of 0.3 - 4.0V/ns.
4. All values specified by design characterization.
5. Please see Section 3.3 for maximum allowable overshoot.
6. Ringback between GTLREF + 100 mV and GTLREF
2. Unless otherwise noted, all specifications in this table apply to all Pentium 4 processor frequencies.
3. Specifications are for the edge rate of 0.3 - 4.0V/ns.
4. All values specified by design characterization.
5. Please see Section 3.3 for maximum allowable overshoot.
6. Ringback between GTLREF + 100 mV and GTLREF
- 100 mV is not supported.
7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other
sources of system noise.
Figure 12. BCLK[1:0] Signal Integrity Waveform
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
Table 17. Ringback Specifications for AGTL+, Asynchronous GTL+,
and TAP Signal Groups
Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
All Signals
0
→
1
GTLREF + 0.100
V
1,2,3,4,5,6,7
All Signals
1
→
0
GTLREF - 0.100
V
1,2,3,4,5,6,7