Intel Pentium 4 672 HH80547PG1122MH User Manual
Product codes
HH80547PG1122MH
Intel
®
Pentium
®
4 Processor in the 423-pin Package
7
1.0
Introduction
The Intel
®
Pentium
®
4 Processor in the 423-pin Package socket with Intel
®
NetBurst
micro-
architechture is based on a new 32-bit micro-architecture that operates at significantly higher clock
speeds and delivers performance levels that are significantly higher than previous generations of
IA-32 processors. While based on the Intel
speeds and delivers performance levels that are significantly higher than previous generations of
IA-32 processors. While based on the Intel
®
NetBurst
micro-architecture, it still maintains the
tradition of compatibility with IA-32 software. The Intel NetBurst micro-architecture features
include hyper pipelined technology, a rapid execution engine, a 400 MHz system bus, and an
execution trace cache. The hyper pipelined technology doubles the pipeline depth in the Pentium 4
processor, allowing the processor to reach much higher core frequencies. The rapid execution
engine allows the two integer ALUs in the processor to run at twice the core frequency, which
allows many integer instructions to execute in 1/2 clock tick. The 400 MHz system bus is a quad-
pumped bus running off a 100 MHz system clock making 3.2 GB/sec data transfer rates possible.
The execution trace cache is a level 1 cache that stores approximately 12k decoded micro-
operations, which removes the decoder from the main execution path, thereby increasing
performance.
include hyper pipelined technology, a rapid execution engine, a 400 MHz system bus, and an
execution trace cache. The hyper pipelined technology doubles the pipeline depth in the Pentium 4
processor, allowing the processor to reach much higher core frequencies. The rapid execution
engine allows the two integer ALUs in the processor to run at twice the core frequency, which
allows many integer instructions to execute in 1/2 clock tick. The 400 MHz system bus is a quad-
pumped bus running off a 100 MHz system clock making 3.2 GB/sec data transfer rates possible.
The execution trace cache is a level 1 cache that stores approximately 12k decoded micro-
operations, which removes the decoder from the main execution path, thereby increasing
performance.
Improved features within the Intel NetBurst micro-architecture include advanced dynamic
execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming
SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and
branch prediction internal to the processor. The advanced transfer cache is a 256kB, on-die level 2
cache with increased bandwidth over previous micro-architectures. The floating point and multi-
media units have been improved by making the registers 128 bits wide and adding a separate
register for data movement. Finally, SSE2 adds 144 new instructions for double-precision floating
point, SIMD integer, and memory management.
execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming
SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and
branch prediction internal to the processor. The advanced transfer cache is a 256kB, on-die level 2
cache with increased bandwidth over previous micro-architectures. The floating point and multi-
media units have been improved by making the registers 128 bits wide and adding a separate
register for data movement. Finally, SSE2 adds 144 new instructions for double-precision floating
point, SIMD integer, and memory management.
The Streaming SIMD Extensions 2 enable break-through levels of performance in multimedia
applications including 3-D graphics, video decoding/encoding, and speech recognition. The new
packed double-precision floating-point instructions enhance performance for applications that
require greater range and precision, including scientific and engineering applications and advanced
3-D geometry techniques, such as ray tracing.
applications including 3-D graphics, video decoding/encoding, and speech recognition. The new
packed double-precision floating-point instructions enhance performance for applications that
require greater range and precision, including scientific and engineering applications and advanced
3-D geometry techniques, such as ray tracing.
The Pentium 4 processor supports uni-processor configurations only. As a result of this integration,
the return to Pin Grid Array (PGA) style processor packaging is possible. The same manageability
features which are included in Intel
the return to Pin Grid Array (PGA) style processor packaging is possible. The same manageability
features which are included in Intel
®
Pentium
®
III processors are included on Pentium 4 processors
with the addition of Thermal Monitor. The Thermal Monitor allows systems to be designed for
anticipated processor thermals as opposed to worst case with no performance degradation
expected. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep
have also been retained for power management capabilities.
anticipated processor thermals as opposed to worst case with no performance degradation
expected. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep
have also been retained for power management capabilities.
New heat sinks, heat sink retention mechanisms, and sockets are required for the Pentium 4
processor in the 423-pin package. The socket for the Pentium 4 processor in the 423-pin package is
called the 423-Pin Socket in this and other documentation. Through-hole ZIF technology will be
used for the 423-Pin Socket. Reference heat sink and retention mechanism designs have been
developed with manufacturability as a high priority. Hence, mechanical assembly can be completed
from the top of the motherboard and should not require any special tooling.
processor in the 423-pin package. The socket for the Pentium 4 processor in the 423-pin package is
called the 423-Pin Socket in this and other documentation. Through-hole ZIF technology will be
used for the 423-Pin Socket. Reference heat sink and retention mechanism designs have been
developed with manufacturability as a high priority. Hence, mechanical assembly can be completed
from the top of the motherboard and should not require any special tooling.
The Pentium 4 processor in the 423-pin package uses a new scalable system bus protocol referred
to as the “system bus” in this document. The Pentium 4 processor system bus utilizes a split-
transaction, deferred reply protocol similar to that of the P6 processor family system bus, but is not
compatible with the P6 processor family system bus. The system bus uses Source-Synchronous
Transfer (SST) of address and data to improve performance. Whereas the P6 processor family
transfers data once per bus clock, the Pentium 4 processor transfers data four times per bus clock
to as the “system bus” in this document. The Pentium 4 processor system bus utilizes a split-
transaction, deferred reply protocol similar to that of the P6 processor family system bus, but is not
compatible with the P6 processor family system bus. The system bus uses Source-Synchronous
Transfer (SST) of address and data to improve performance. Whereas the P6 processor family
transfers data once per bus clock, the Pentium 4 processor transfers data four times per bus clock