Intel 41210 User Manual
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Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Introduction
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Up to two downstream delayed (memory read, I/O read/write and configuration read/write)
transactions
transactions
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Tunable inbound read prefetch algorithm for PCI MRM/MRL commands
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Device hiding support for secondary PCI devices
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Secondary bus private memory support via opaque memory region
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Local initialization via SMBus
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Secondary side initialization via Type 0 configuration cycles
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Full peer-to-peer read/write capability between the two secondary PCI segments
1.3
Power Management
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Support for PCI PM 1.1-compatible D0, D3hot and D3cold device power states
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Support for PME# event propagation on behalf of PCI devices
1.4
SMBus Interface
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Compatible with System Management Bus Specification, Revision 2.0
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Slave-mode operation only
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Full read/write access to all configuration registers
1.5
JTAG
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IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a