Intel 41210 User Manual
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Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Clock and Reset
10.2.1
PERST# Reset Mechanism
All the voltage sources in the system are tracked by a system component that asserts the PERST#
signal only after all the voltages have been stable for some predetermined time. The 41210 receives
the PERST# signal as an asynchronous input, meaning that there is no assumed relationship
between the assertion or the de-assertion of PERST# and the reference clock. While the PERST# is
de-asserted, the 41210 holds all logic in reset.
signal only after all the voltages have been stable for some predetermined time. The 41210 receives
the PERST# signal as an asynchronous input, meaning that there is no assumed relationship
between the assertion or the de-assertion of PERST# and the reference clock. While the PERST# is
de-asserted, the 41210 holds all logic in reset.
The PERST# reset clears all internal state machines and logic, and initializes all registers to their
default states, including “sticky” error bits that are persistent through all other reset classes. To
eliminate potential system-reliability problems, all devices are also required to either tristate their
outputs or to drive them to safe levels during such a power-on reset.
default states, including “sticky” error bits that are persistent through all other reset classes. To
eliminate potential system-reliability problems, all devices are also required to either tristate their
outputs or to drive them to safe levels during such a power-on reset.
The 41210 keeps PCIRST# asserted for a minimum of 320 ms after the deassertion of PERST#.
Refer to the PCI Express* Specification, Revision 1.0a for details of the relationship between
PERST# assertion and the stability of the clocks and power at the inputs of the 41210.
PERST# assertion and the stability of the clocks and power at the inputs of the 41210.
10.2.2
RSTIN# Reset Mechanism
As soon as the system is up and running, a full system reset may be required to recover from
system-error conditions related to various device or subsystem failures. The RSTIN# reset
mechanism is a hot-reset mechanism that accomplishes this recovery without clearing the “sticky”
error-status bits which track the cause of the error conditions of the device or subsystem.
system-error conditions related to various device or subsystem failures. The RSTIN# reset
mechanism is a hot-reset mechanism that accomplishes this recovery without clearing the “sticky”
error-status bits which track the cause of the error conditions of the device or subsystem.
A hot reset can be initiated by asserting the RSTIN# signal. This signal is treated as an
asynchronous input to the 41210, meaning that there is no assumed relationship between the host
reference clock and the assertion or the de-assertion of RSTIN#.
asynchronous input to the 41210, meaning that there is no assumed relationship between the host
reference clock and the assertion or the de-assertion of RSTIN#.
When the 41210 goes through a reset due to RSTIN# assertion, the link goes down, which is
interpreted by the upstream component as a surprise extraction which may cause system instability.
interpreted by the upstream component as a surprise extraction which may cause system instability.
The 41210 keeps PCIRST# asserted for a minimum of 320 ms after the deassertion of RSTIN#.
10.2.3
PCI Express* Reset Mechanism
There is no reset signal on the PCI Express*, and all reset communication is in-band. The upstream
PCI Express* device communicates the fact that it is entering and coming out of a reset using
messages. The 41210 responds by also going through a reset. In accordance with the PCI Express*
protocol, this incoming message is asynchronous to the reference clock.
PCI Express* device communicates the fact that it is entering and coming out of a reset using
messages. The 41210 responds by also going through a reset. In accordance with the PCI Express*
protocol, this incoming message is asynchronous to the reference clock.
When the upstream device puts the 41210 Bridge in reset through the in-band reset mechanism, the
41210 resets its core and PCI interfaces. Sticky bits are reserved
41210 resets its core and PCI interfaces. Sticky bits are reserved
The 41210 keeps PCIRST# asserted for a minimum of 320 ms after the deassertion of the PCI
Express* in-band reset message.
Express* in-band reset message.