Nxp Semiconductors p89lpc9321 um10310 User Manual

UM10310_1

© NXP B.V. 2008. All rights reserved.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in 
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global 
enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by 
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An 
interrupt service routine in progress can be interrupted by a higher priority interrupt, but 
not by another interrupt of the same or lower priority. The highest priority interrupt service 
cannot be interrupted by any other interrupt source. If two requests of different priority 
levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an 
internal polling sequence determines which request is serviced. This is called the 
arbitration ranking. Note that the arbitration ranking is only used for pending requests of 
the same priority level. 

 summarizes the interrupt sources, flag bits, vector 

addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may 
wake-up the CPU from a Power-down mode.

 

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every 
interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of 
four levels, as shown in 

.

The P89LPC9321 has two external interrupt inputs in addition to the Keypad Interrupt 
function. The two interrupt inputs are identical to those present on the standard 80C51 
microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by 
clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is 
triggered by a low level detected at the INTn pin. If ITn = 1, external interrupt n is edge 
triggered. In this mode if consecutive samples of the INTn pin show a high level in one 
cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing 
an interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high or 
low level should be held for at least one machine cycle to ensure proper sampling. If the 
external interrupt is edge-triggered, the external source has to hold the request pin high 
for at least one machine cycle, and then hold it low for at least one machine cycle. This is 
to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is 
automatically cleared by the CPU when the service routine is called.

0

0

Level 0 (lowest priority)

0

1

Level 1

1

0

Level 2

1

1

Level 3