Daewoo dsc-3220e-3220l User Manual
Service manual SC-150
-19-
Horizontal scaling ( 0.25 to 4 )
Panoramavision
Black-level expander
Dynamic peaking
Soft limiter (gamma correction)
Colour transient improvement
Programmable RGB matrix
Analogu e RGB/Fastblank input
Half-contrast switch
Picture frame generator
Scan velocity modulation output
High-performance H/V deflection
Angle and bow correction
Separate ADC for tube measurements
EHT compensation
Panoramavision
Black-level expander
Dynamic peaking
Soft limiter (gamma correction)
Colour transient improvement
Programmable RGB matrix
Analogu e RGB/Fastblank input
Half-contrast switch
Picture frame generator
Scan velocity modulation output
High-performance H/V deflection
Angle and bow correction
Separate ADC for tube measurements
EHT compensation
4-1-3- -Controller
8-bit, 10-Mhz CPU (65C02)
96 kB program ROM on chip
1 kB program RAM on chip
memory banking
16-input, 16-level interrupt controller
patch module for 10 ROM locations
two 16-bit reloadable timers
capture compare module
watchdog timer
14-bit PWM for voltage synthesis
Four 8-bit PWMs
10-bit ADC with 15:1 input MUX
I2C bus master interface
24 programmable I/O ports
80C51 -controller core standard instruction set and timing
1 s machine cycle
32-128Kx8-bit late programmed ROM
3-12Kx8-bit Auxiliary RAM (shared with Display and Acquisition)
Interrupt controller for individual enable/disable with two level priority
Two 16-bit Timer/Counter registers
WatchDog timer
Auxiliary RAM page pointer
16-bit Data pointer
IDLE and Power Down (PD) mode
14 bits PWM for Voltage Synthesis Tuning
8-bit A/D converter
4 pins which can be programmed as general I/O pin, ADC input or PWM (6-bit) output
8-bit, 10-Mhz CPU (65C02)
96 kB program ROM on chip
1 kB program RAM on chip
memory banking
16-input, 16-level interrupt controller
patch module for 10 ROM locations
two 16-bit reloadable timers
capture compare module
watchdog timer
14-bit PWM for voltage synthesis
Four 8-bit PWMs
10-bit ADC with 15:1 input MUX
I2C bus master interface
24 programmable I/O ports
80C51 -controller core standard instruction set and timing
1 s machine cycle
32-128Kx8-bit late programmed ROM
3-12Kx8-bit Auxiliary RAM (shared with Display and Acquisition)
Interrupt controller for individual enable/disable with two level priority
Two 16-bit Timer/Counter registers
WatchDog timer
Auxiliary RAM page pointer
16-bit Data pointer
IDLE and Power Down (PD) mode
14 bits PWM for Voltage Synthesis Tuning
8-bit A/D converter
4 pins which can be programmed as general I/O pin, ADC input or PWM (6-bit) output
4-1-4- Teletext Features
Four programmable video inputs
Adapt ive data slicer
Signal quality detection
WS T, PDC, VPS, and WSS acquisition
Four programmable video inputs
Adapt ive data slicer
Signal quality detection
WS T, PDC, VPS, and WSS acquisition