Contec SPI-8451-LLVA User Manual

8. BIOS Setup

SPI-8451-LLVA, SPI-8452-LLVA, SPI-8451-LVA

111

POST Codes

POST

(hex)

Description

CFh

Test CMOS R/W functionality.

C0h

Early chipset initialization:

-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers

C1h

Detect memory

-Auto-detection of DRAM size, type and ECC.
-Auto-detection of L2 cache (socket 7 or below)

C3h

Expand compressed BIOS code to DRAM

C5h

Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.

01h

Expand the Xgroup codes locating in physical address 1000:0

02h

Reserved

03h

Initial Superio_Early_Init switch.

04h

Reserved

05h

Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.

06h

Expand the Xgroup codes locating in physical address 1000:0

07h

Reserved

08h

Initial Superio_Early_Init switch.

09h

Reserved

0Ah

1. Blank out screen
2. Clear CMOS error flag

0Bh

Reserved

0Ch

1. Clear 8042 interface
2. Initialize 8042 self-test

0Dh

Reserved

0Eh

Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the
speaker.

0Fh

Reserved

10h

Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for
ESCD & DMI support.

11h

Reserved

12h

Use walking 1’s algorithm to check out interface in CMOS circuitry. Also set real-time clock
power status, and then check for override.

13h

Reserved

14h

Program chipset default values into chipset. Chipset default values are MODBINable by OEM
customers.

15h

Reserved

16h

Initial Early_Init_Onboard_Generator switch.

17h

Reserved

18h

Detect CPU information including brand, SMI type (Cyrix or Intel

) and CPU level (586 or

686).

19h

Reserved

1Ah

Reserved

1Bh

Initial interrupts vector table. If no special specified, all H/W interrupts are directed to
SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR.

1Ch

Reserved

1Dh

Initial EARLY_PM_INIT switch.

1Eh

Reserved

1Fh

Load keyboard matrix (notebook platform)