Intel CM8063501287403 User Manual

Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

123

Datasheet Volume One of Two

 

MEM_HOT_C01_N
MEM_HOT_C23_N

Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N 

signals have two modes of operation – input and output mode.

Input mode is externally asserted and is used to detect external 

events such as VR_HOT# from the memory voltage regulator and 

causes the processor to throttle the appropriate memory channels.

Output mode is asserted by the processor known as level mode. In 

level mode, the output indicates that a particular branch of 

memory subsystem is hot.

MEM_HOT_C01_N is used for memory channels 0 & 1 while 

MEM_HOT_C23_N is used for memory channels 2 & 3.

PMSYNC

Power Management Sync. A sideband signal to communicate 

power management status from the Platform Controller Hub (PCH) 

to the processor.

PROCHOT_N

PROCHOT_N will go active when the processor temperature 

monitoring sensor detects that the processor has reached its 

maximum safe operating temperature. This indicates that the 

processor Thermal Control Circuit has been activated, if enabled. 

This signal can also be driven to the processor to activate the 

Thermal Control Circuit. This signal is sampled after PWRGOOD 

assertion.
If PROCHOT_N is asserted at the deassertion of RESET_N, the 

processor will tristate its outputs.

PWRGOOD

Power Good is a processor input. The processor requires this signal 

to be a clean indication that BCLK, VTTA/VTTD, VSA, VCCPLL, and 

VCCD_01 and VCCD_23 supplies are stable and within their 

specifications.

“Clean” implies that the signal will remain low (capable of sinking 

leakage current), without glitches, from the time that the power 

supplies are turned on until they come within specification. The 

signal must then transition monotonically to a high state.

PWRGOOD can be driven inactive at any time, but clocks and 

power must again be stable before a subsequent rising edge of 

PWRGOOD. PWRGOOD transitions from inactive to active when all 

supplies except VCC are stable. VCC has a VBOOT of zero volts and 

is not included in PWRGOOD indication in this phase. However, for 

the active to inactive transition, if any CPU power supply (VCC, 

VTTA/VTTD, VSA, VCCD, or VCCPLL) is about to fail or is out of 

regulation, the PWRGOOD is to be negated.

The signal must be supplied to the processor; it is used to protect 

internal circuits against voltage sequencing issues. It should be 

driven high throughout boundary scan operation.

Note: VCC has a Vboot setting of 0.0V and is not included in the 

PWRGOOD indication and VSA has a Vboot setting of 0.9V. Refer to 

the compatible VR12.0 PWM controller.

RESET_N

Asserting the RESET_N signal resets the processor to a known 

state and invalidates its internal caches without writing back any of 

their contents. Note some PLL, Intel QuickPath Interconnect and 

error states are not effected by reset and only PWRGOOD forces 

them to a known state.

RSVD

RESERVED. All signals that are RSVD must be left unconnected on 

the board. Refer to 

 

for details. 

SAFE_MODE_BOOT

Safe mode boot Strap. SAFE_MODE_BOOT allows the processor to 

wake up safely by disabling all clock gating, this allows BIOS to 

load registers or patches if required. This signal is sampled after 

PWRGOOD assertion. The signal is pulled down on the die, refer to 

 for details.