Intel CM8064601466003 User Manual



 Specification Update

45

Problem:

Under certain internal timing conditions, the processor might not properly exit package 
C7 leading to a hang.

Implication:

Due to this erratum, the package C7 state may not be reliable. Intel has not observed 
this erratum with any commercially available system.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Table of Changes.

Problem:

Under a complex set of internal timing conditions and system events, software using 
the Intel TSX (Transactional Synchronization Extensions) instructions may observe 
unpredictable system behavior.

Implication:

This erratum may result in unpredictable system behavior. Intel has not observed this 
erratum with any commercially available system.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Table of Changes.

Problem:

Under certain stressful conditions while running at ring ratios higher than 30, the 
processor may experience a spurious LLC machine check as indicated by 
IA32_MCi_STATUS.MCACOD (bits [15:0]) with value 000x 0001 0000 1010 (where x is 
0 or 1).

Implication:

When this erratum occurs, an uncorrectable LLC error will be logged and the system 
may hang or restart.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Table of Changes.

Problem:

Under the following conditions:

1. A read-modify-write instruction’s memory source/destination (e.g., ADD memory, reg) 

crossing a cache line boundary.

2. That instruction executing without fault.

3. While the read-modify-write instruction is executing, one or more of the following page 

table attributes associated with its memory operand are modified:

a.

the D (dirty) flag was 0 when the instruction was initiated but was concurrently set to 1, and/

or

b. one of the relevant R/W flags was 0 when the instruction was initiated but was 

concurrently set to 1, and/or

c. if the read-modify-write instruction executes at CPL = 3 and one of the relevant U/

S flags was 0 when the instruction was initiated but was concurrently set to 1.

4. A subsequent instruction executing within a narrow timing window that experiences a 

page fault

5. There is no serializing instruction between the read-modify-write instruction and the 

faulting instruction.