Intel architecture ia-32 User Manual
Vol. 3A 5-49
INTERRUPT AND EXCEPTION HANDLING
•
A selector from a TSS involved in a task switch.
•
IDT vector number.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that generated the exception.
Program State Change
In general, a program-state change does not accompany a general-protection exception, because
the invalid instruction or operation is not executed. An exception handler can be designed to
correct all of the conditions that cause general-protection exceptions and restart the program or
task without any loss of program continuity.
the invalid instruction or operation is not executed. An exception handler can be designed to
correct all of the conditions that cause general-protection exceptions and restart the program or
task without any loss of program continuity.
If a general-protection exception occurs during a task switch, it can occur before or after the
commit-to-new-task point (see Section 6.3, “Task Switching”). If it occurs before the commit
point, no program state change occurs. If it occurs after the commit point, the processor will load
all the state information from the new TSS (without performing any additional limit, present, or
type checks) before it generates the exception. The general-protection exception handler should
thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and
GS registers without causing another exception. (See the Program State Change description for
“Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how
to handle this situation.)
commit-to-new-task point (see Section 6.3, “Task Switching”). If it occurs before the commit
point, no program state change occurs. If it occurs after the commit point, the processor will load
all the state information from the new TSS (without performing any additional limit, present, or
type checks) before it generates the exception. The general-protection exception handler should
thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and
GS registers without causing another exception. (See the Program State Change description for
“Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how
to handle this situation.)
General Protection Exception in 64-bit Mode
The following conditions cause general-protection exceptions in 64-bit mode:
•
If the memory address is in a non-canonical form.
•
If a segment descriptor memory address is in non-canonical form.
•
If the target offset in a destination operand of a call or jmp is in a non-canonical form.
•
If a code segment or 64-bit call gate overlaps non-canonical space.
•
If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the
L-bit set and the D-bit clear.
L-bit set and the D-bit clear.
•
If the EFLAGS.NT bit is set in IRET.
•
If the stack segment selector of IRET is null when going back to compatibility mode.
•
If the stack segment selector of IRET is null going back to CPL3 and 64-bit mode.
•
If a null stack segment selector RPL of IRET is not equal to CPL going back to non-CPL3
and 64-bit mode.
and 64-bit mode.
•
If the proposed new code segment descriptor of IRET has both the D-bit and the L-bit set.
•
If the segment descriptor pointed to by the segment selector in the destination operand is a
code segment and it has both the D-bit and the L-bit set.
code segment and it has both the D-bit and the L-bit set.