Intel architecture ia-32 User Manual
6-6 Vol. 3A
TASK MANAGEMENT
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EFLAGS register field — State of the EFAGS register prior to the task switch.
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EIP (instruction pointer) field — State of the EIP register prior to the task switch.
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Previous task link field — Contains the segment selector for the TSS of the previous task
(updated on a task switch that was initiated by a call, interrupt, or exception). This field
(which is sometimes called the back link field) permits a task switch back to the previous
task by using the IRET instruction.
(updated on a task switch that was initiated by a call, interrupt, or exception). This field
(which is sometimes called the back link field) permits a task switch back to the previous
task by using the IRET instruction.
The processor reads the static fields, but does not normally change them. These fields are set up
when a task is created. The following are static fields:
when a task is created. The following are static fields:
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LDT segment selector field — Contains the segment selector for the task's LDT.
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CR3 control register field — Contains the base physical address of the page directory to
be used by the task. Control register CR3 is also known as the page-directory base register
(PDBR).
be used by the task. Control register CR3 is also known as the page-directory base register
(PDBR).
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Privilege level-0, -1, and -2 stack pointer fields — These stack pointers consist of a
logical address made up of the segment selector for the stack segment (SS0, SS1, and SS2)
and an offset into the stack (ESP0, ESP1, and ESP2). Note that the values in these fields
are static for a particular task; whereas, the SS and ESP values will change if stack
switching occurs within the task.
logical address made up of the segment selector for the stack segment (SS0, SS1, and SS2)
and an offset into the stack (ESP0, ESP1, and ESP2). Note that the values in these fields
are static for a particular task; whereas, the SS and ESP values will change if stack
switching occurs within the task.
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T (debug trap) flag (byte 100, bit 0) — When set, the T flag causes the processor to raise
a debug exception when a task switch to this task occurs (see Section 18.3.1.5, “Task-
Switch Exception Condition”).
a debug exception when a task switch to this task occurs (see Section 18.3.1.5, “Task-
Switch Exception Condition”).
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I/O map base address field — Contains a 16-bit offset from the base of the TSS to the I/O
permission bit map and interrupt redirection bitmap. When present, these maps are stored
in the TSS at higher addresses. The I/O map base address points to the beginning of the I/O
permission bit map and the end of the interrupt redirection bit map. See Chapter 13,
“Input/Output,” in the IA-32 Intel® Architecture Software Developer’s Manual, Volume 1,
for more information about the I/O permission bit map. See Section 15.3, “Interrupt and
Exception Handling in Virtual-8086 Mode,” for a detailed description of the interrupt
redirection bit map.
permission bit map and interrupt redirection bitmap. When present, these maps are stored
in the TSS at higher addresses. The I/O map base address points to the beginning of the I/O
permission bit map and the end of the interrupt redirection bit map. See Chapter 13,
“Input/Output,” in the IA-32 Intel® Architecture Software Developer’s Manual, Volume 1,
for more information about the I/O permission bit map. See Section 15.3, “Interrupt and
Exception Handling in Virtual-8086 Mode,” for a detailed description of the interrupt
redirection bit map.
If paging is used:
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Avoid placing a page boundary in the part of the TSS that the processor reads during a task
switch (the first 104 bytes). The processor may not correctly perform address translations
if a boundary occurs in this area. During a task switch, the processor reads and writes into
the first 104 bytes of each TSS (using contiguous physical addresses beginning with the
physical address of the first byte of the TSS). So, after TSS access begins, if part of the 104
bytes is not physically contiguous, the processor will access incorrect information without
generating a page-fault exception.
switch (the first 104 bytes). The processor may not correctly perform address translations
if a boundary occurs in this area. During a task switch, the processor reads and writes into
the first 104 bytes of each TSS (using contiguous physical addresses beginning with the
physical address of the first byte of the TSS). So, after TSS access begins, if part of the 104
bytes is not physically contiguous, the processor will access incorrect information without
generating a page-fault exception.
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Pages corresponding to the previous task’s TSS, the current task’s TSS, and the descriptor
table entries for each all should be marked as read/write.
table entries for each all should be marked as read/write.
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Task switches are carried out faster if the pages containing these structures are present in
memory before the task switch is initiated.
memory before the task switch is initiated.