Intel architecture ia-32 User Manual
8-38 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Its value in the PPR is computed as follows:
IF TPR[7:4]
≥ ISRV[7:4]
THEN
PPR[7:0]
← TPR[7:0]
ELSE
PPR[7:4]
← ISRV[7:4]
PPR[3:0]
← 0
Here, the ISRV value is the vector number of the highest priority ISR bit that is set, or 00H if no
ISR bit is set. Essentially, the processor priority is set to either to the highest priority pending
interrupt in the ISR or to the current task priority, whichever is higher.
ISR bit is set. Essentially, the processor priority is set to either to the highest priority pending
interrupt in the ISR or to the current task priority, whichever is higher.
8.8.4
Interrupt Acceptance for Fixed Interrupts
The local APIC queues the fixed interrupts that it accepts in one of two interrupt pending regis-
ters: the interrupt request register (IRR) or in-service register (ISR). These two 256-bit read-only
registers are shown in Figure 8-20. The 256 bits in these registers represent the 256 possible
vectors; vectors 0 through 15 are reserved by the APIC (see also: Section 8.5.2, “Valid Interrupt
Vectors”).
ters: the interrupt request register (IRR) or in-service register (ISR). These two 256-bit read-only
registers are shown in Figure 8-20. The 256 bits in these registers represent the 256 possible
vectors; vectors 0 through 15 are reserved by the APIC (see also: Section 8.5.2, “Valid Interrupt
Vectors”).
NOTE
All interrupts with an NMI, SMI, INIT, ExtINT, start-up, or INIT-deassert
delivery mode bypass the IRR and ISR registers and are sent directly to the
processor core for servicing.
delivery mode bypass the IRR and ISR registers and are sent directly to the
processor core for servicing.
Figure 8-19. Processor Priority Register (PPR)
31
0
7
8
Reserved
Address: FEE0 00A0H
Value after reset: 0H
Value after reset: 0H
Processor Priority Sub-Class
Processor Priority
4 3