Intel architecture ia-32 User Manual
10-24 Vol. 3A
MEMORY CACHE CONTROL
10.10 STORE BUFFER
IA-32 processors temporarily store each write (store) to memory in a store buffer. The store
buffer improves processor performance by allowing the processor to continue executing instruc-
tions without having to wait until a write to memory and/or to a cache is complete. It also allows
writes to be delayed for more efficient use of memory-access bus cycles.
buffer improves processor performance by allowing the processor to continue executing instruc-
tions without having to wait until a write to memory and/or to a cache is complete. It also allows
writes to be delayed for more efficient use of memory-access bus cycles.
In general, the existence of the store buffer is transparent to software, even in systems that use
multiple processors. The processor ensures that write operations are always carried out in
program order. It also insures that the contents of the store buffer are always drained to memory
in the following situations:
multiple processors. The processor ensures that write operations are always carried out in
program order. It also insures that the contents of the store buffer are always drained to memory
in the following situations:
•
When an exception or interrupt is generated.
•
(Pentium 4, Intel Xeon, and P6 family processors only) When a serializing instruction is
executed.
executed.
•
When an I/O instruction is executed.
•
When a LOCK operation is performed.
•
(Pentium 4, Intel Xeon, and P6 family processors only) When a BINIT operation is
performed.
performed.
•
(Pentium III, Pentium 4, and Intel Xeon processors only) When using an SFENCE
instruction to order stores.
instruction to order stores.
•
(Pentium 4 and Intel Xeon processors only) When using an MFENCE instruction to order
stores.
stores.
The discussion of write ordering in Section 7.2, “Memory Ordering,” gives a detailed descrip-
tion of the operation of the store buffer.
tion of the operation of the store buffer.
10.11 MEMORY TYPE RANGE REGISTERS (MTRRS)
The following section pertains only to the Pentium 4, Intel Xeon, and P6 family processors.
The memory type range registers (MTRRs) provide a mechanism for associating the memory
types (see Section 10.3, “Methods of Caching Available”) with physical-address ranges in
system memory. They allow the processor to optimize operations for different types of memory
such as RAM, ROM, frame-buffer memory, and memory-mapped I/O devices. They also
simplify system hardware design by eliminating the memory control pins used for this function
on earlier IA-32 processors and the external logic needed to drive them.
types (see Section 10.3, “Methods of Caching Available”) with physical-address ranges in
system memory. They allow the processor to optimize operations for different types of memory
such as RAM, ROM, frame-buffer memory, and memory-mapped I/O devices. They also
simplify system hardware design by eliminating the memory control pins used for this function
on earlier IA-32 processors and the external logic needed to drive them.
The MTRR mechanism allows up to 96 memory ranges to be defined in physical memory, and
it defines a set of model-specific registers (MSRs) for specifying the type of memory that is
contained in each range. Table 10-8 shows the memory types that can be specified and their
properties; Figure 10-3 shows the mapping of physical memory with MTRRs. See Section 10.3,
“Methods of Caching Available,” for a more detailed description of each memory type.
it defines a set of model-specific registers (MSRs) for specifying the type of memory that is
contained in each range. Table 10-8 shows the memory types that can be specified and their
properties; Figure 10-3 shows the mapping of physical memory with MTRRs. See Section 10.3,
“Methods of Caching Available,” for a more detailed description of each memory type.
Following a hardware reset, a Pentium 4, Intel Xeon, or P6 family processor disables all the
fixed and variable MTRRs, which in effect makes all of physical memory uncachable. Initial-
fixed and variable MTRRs, which in effect makes all of physical memory uncachable. Initial-