Intel architecture ia-32 User Manual

12-2 Vol. 3A

If the processor attempts to execute an unsupported SSE/SSE2/SSE3 instruction, the processor
will generate an invalid-opcode exception (#UD).

Before an operating system or executive attempts to use SSE/SSE2/SSE3 extensions, it should
check that support is present on the processor. To make this check, execute CPUID with an argu-
ment of 1 in the EAX register. Make sure:

•

CPUID.1:EDX.SSE[bit 25] = 1

•

CPUID.1:EDX.SSE2[bit 26] = 1

•

CPUID.1:ECX.SSE3[bit 0] = 1

A separate check must be made to insure that the processor supports FXSAVE and FXRSTOR.
To make this check, execute CPUID with an argument of 1 in the EAX register. Make sure:

•

CPUID.1:EDX.FXSR[bit 24] = 1 

The operating system or executive should carry out the following steps to set up
SSE/SSE2/SSE3 extensions for use by application programs:

1.

Set CR4.OSFXSR[bit 9] = 1. Setting this flag assumes that the operating system provides
facilities for saving and restoring SSE/SSE2/SSE3 states using FXSAVE and FXRSTOR
instructions. These instructions are commonly used to save the SSE/SSE2/SSE3 state
during task switches and when invoking the SIMD floating-point exception (#XF) handler
(see Section 12.4, “Saving the SSE/SSE2/SSE3 State on Task or Context Switches,” and
Section 12.1.6, “Providing an Handler for the SIMD Floating-Point Exception (#XF),”
respectively). 

If the processor does not support the FXSAVE and FXRSTOR instructions, attempting to
set the OSFXSR flag will cause an exception (#GP) to be generated.

2.

Set CR4.OSXMMEXCPT[bit 10] = 1. Setting this flag assumes that the operating system
provides an SIMD floating-point exception (#XF) handler (see Section 12.1.6, “Providing
an Handler for the SIMD Floating-Point Exception (#XF)”).