Intel architecture ia-32 User Manual

2-4 Vol. 3A

Local Descriptor

Table (LDT)

CR1

CR2

CR3

CR4

CR0

Global Descriptor

Table (GDT)

Interrupt Descriptor

Table (IDT)

IDTR

GDTR

Interrupt Gate

Trap Gate

LDT Desc.

TSS Desc.

Code

Stack

Code

Stack

Code

Stack

Current TSS

Code

Stack

Interr. Handler

Interrupt Handler

Exception Handler

Protected Procedure

TR

Call-Gate

Segment Selector

Linear Address

PML4

PML4.

Linear Address Space

Linear Addr.

0

Seg. Desc.

Segment Sel.

Code, Data or Stack 
Segment (Base =0)

Interrupt

Vector

Seg. Desc.

Seg. Desc.

NULL

Call Gate

Task-State

Segment (TSS)

Seg. Desc.

NULL

NULL

Segment Selector

Linear Address

Task Register

CR3*

Page

LDTR

This page mapping example is for 4-KByte pages

and 40-bit physical address size.

Register

*Physical Address

Physical Address

CR8

Control Register

RFLAGS

Offset

Table

Directory

Page Table

Entry

Physical

Addr.

Page Tbl

Entry

Page Dir.

Pg. Dir. Ptr. 

PML4 Dir. Pointer

Pg. Dir.

Entry

Interrupt Gate

IST