Intel architecture ia-32 User Manual
15-14 Vol. 3A
8086 EMULATION
15.2.7
Sensitive Instructions
When an IA-32 processor is running in virtual-8086 mode, the CLI, STI, PUSHF, POPF, INT n,
and IRET instructions are sensitive to IOPL. The IN, INS, OUT, and OUTS instructions, which
are sensitive to IOPL in protected mode, are not sensitive in virtual-8086 mode.
and IRET instructions are sensitive to IOPL. The IN, INS, OUT, and OUTS instructions, which
are sensitive to IOPL in protected mode, are not sensitive in virtual-8086 mode.
The CPL is always 3 while running in virtual-8086 mode; if the IOPL is less than 3, an attempt
to use the IOPL-sensitive instructions listed above triggers a general-protection exception
(#GP). These instructions are sensitive to IOPL to give the virtual-8086 monitor a chance to
emulate the facilities they affect.
to use the IOPL-sensitive instructions listed above triggers a general-protection exception
(#GP). These instructions are sensitive to IOPL to give the virtual-8086 monitor a chance to
emulate the facilities they affect.
15.2.8
Virtual-8086 Mode I/O
Many 8086 programs written for non-multitasking systems directly access I/O ports. This prac-
tice may cause problems in a multitasking environment. If more than one program accesses the
same port, they may interfere with each other. Most multitasking systems require application
programs to access I/O ports through the operating system. This results in simplified, centralized
control.
tice may cause problems in a multitasking environment. If more than one program accesses the
same port, they may interfere with each other. Most multitasking systems require application
programs to access I/O ports through the operating system. This results in simplified, centralized
control.
The processor provides I/O protection for creating I/O that is compatible with the environment
and transparent to 8086 programs. Designers may take any of several possible approaches to
protecting I/O ports:
and transparent to 8086 programs. Designers may take any of several possible approaches to
protecting I/O ports:
•
Protect the I/O address space and generate exceptions for all attempts to perform I/O
directly.
directly.
•
Let the 8086 program perform I/O directly.
•
Generate exceptions on attempts to access specific I/O ports.
•
Generate exceptions on attempts to access specific memory-mapped I/O ports.
The method of controlling access to I/O ports depends upon whether they are I/O-port mapped
or memory mapped.
or memory mapped.
15.2.8.1
I/O-Port-Mapped I/O
The I/O permission bit map in the TSS can be used to generate exceptions on attempts to access
specific I/O port addresses. The I/O permission bit map of each virtual-8086-mode task deter-
mines which I/O addresses generate exceptions for that task. Because each task may have a
different I/O permission bit map, the addresses that generate exceptions for one task may be
different from the addresses for another task. This differs from protected mode in which, if the
CPL is less than or equal to the IOPL, I/O access is allowed without checking the I/O permission
bit map. See Chapter 13, “Input/Output”, in the IA-32 Intel® Architecture Software Developer’s
Manual, Volume 1, for more information about the I/O permission bit map.
specific I/O port addresses. The I/O permission bit map of each virtual-8086-mode task deter-
mines which I/O addresses generate exceptions for that task. Because each task may have a
different I/O permission bit map, the addresses that generate exceptions for one task may be
different from the addresses for another task. This differs from protected mode in which, if the
CPL is less than or equal to the IOPL, I/O access is allowed without checking the I/O permission
bit map. See Chapter 13, “Input/Output”, in the IA-32 Intel® Architecture Software Developer’s
Manual, Volume 1, for more information about the I/O permission bit map.