Intel architecture ia-32 User Manual

17-4 Vol. 3A

ming for conversion to integer. The remaining two instructions (MONITOR and MWAIT)
accelerate synchronization of threads. SSE3 instructions are described in Chapter 12,
“Programming with Streaming SIMD Extensions 3 (SSE3),” in the IA-32 Intel® Architecture
Software Developer’s Manual, Volume 1, and in the IA-32 Intel® Architecture Software Devel-
oper’s Manual, Volumes 2A & 2B.

Hyper-Threading Technology is an extension to IA-32 architecture. The feature provides two
logical processors that can execute two separate code streams (called threads) concurrently by
using shared resources in single processor core or in a physical package. 

This feature was introduced in the Intel Xeon processor MP and later steppings of the Intel Xeon
processor, and Pentium 4 processors supporting Hyper-Threading Technology. The feature is
also found in the Pentium processor Extreme Edition. See also: Section 7.8, “Intel

The Pentium D processor and Pentium processor Extreme Edition provide two processor cores
in each physical processor package. See also: Section 7.6, “Hyper-Threading and Multi-Core
Technology,” and Section 7.9, “Dual-Core Architecture.”

Dual-core processors may have some processor-specific features. Use CPUID feature flags to
detect the availability features. Note the following:

•

CPUID Brand String — On Pentium processor Extreme Edition, the process will report
the correct brand string only after the correct microcode updates are loaded.

•

Enhanced Intel SpeedStep Technology — This feature is supported in Pentium D
processor but not in Pentium processor Extreme Edition. 

Table 17-1 identifies the instructions introduced into the IA-32 in the Pentium processor and
later IA-32 processors.