Intel architecture ia-32 User Manual

Vol. 3A 3-7

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On processors that support Intel EM64T (CPUID.80000001.EDX[29] = 1), the size of physical
address range is implementation-specific and indicated by CPUID.80000001H. The physical
address size supported by a given implementation is available to IA-32e mode and enhanced
legacy PAE paging. 

See also: Section 3.8.1, “Enhanced Legacy PAE Paging”.

At the system-architecture level in protected mode, the processor uses two stages of address
translation to arrive at a physical address: logical-address translation and linear address space
paging.

Even with the minimum use of segments, every byte in the processor’s address space is accessed
with a logical address. A logical address consists of a 16-bit segment selector and a 32-bit offset
(see Figure 3-5). The segment selector identifies the segment the byte is located in and the offset
specifies the location of the byte in the segment relative to the base address of the segment. 

The processor translates every logical address into a linear address. A linear address is a 32-bit
address in the processor’s linear address space. Like the physical address space, the linear
address space is a flat (unsegmented), 2

32

-byte address space, with addresses ranging from 0 to

FFFFFFFFH. The linear address space contains all the segments and system tables defined for
a system. 

To translate a logical address into a linear address, the processor does the following:

1.

Uses the offset in the segment selector to locate the segment descriptor for the segment in
the GDT or LDT and reads it into the processor. (This step is needed only when a new
segment selector is loaded into a segment register.)

2.

Examines the segment descriptor to check the access rights and range of the segment to
insure that the segment is accessible and that the offset is within the limits of the segment.

3.

Adds the base address of the segment from the segment descriptor to the offset to form a
linear address.