NEC uPD78054 User Manual

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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS

21.4.5 Interrupt request reserve

In some cases, the acknowledgment of the interrupt request is reserved even an interrupt request is generated

during processing of the instruction until the execution of the next instruction is completed. The following shows this

type of instructions (interrupt request reserve instruction).

• MOV

PSW, #byte

• MOV A,

PSW

• MOV

PSW, A

• MOV1

PSW.bit, CY

• MOV1

CY, PSW.bit

• AND1

CY, PSW.bit

• OR1

CY, PSW.bit

• XOR1

CY, PSW.bit

• SET1

PSW.bit

• CLR1

PSW.bit

• RETB

• RETI

• PUSH

PSW

• POP

PSW

• BT

PSW.bit, $addr16

• BF

PSW.bit, $addr16

• BTCLR

PSW.bit, $addr16

• EI

• DI

• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers

Caution

The BRK instruction is not an interrupt request reserve instruction shown above. However, in

the case of software interrupt that is started up with the execution of the BRK instruction, the

IE flag is cleared to 0. Therefore, interrupts are not acknowledged even when a maskable

interrupt request is issued during the execution of the BRK instruction. However, non-maskable

interrupt requests are acknowledged.

Figure 21-17 shows the timing when an interrupt request is reserved.

Figure 21-17. Interrupt Request Hold

Remarks 1. Instruction N: Instruction that holds interrupts requests

2. Instruction M: Instructions other than instruction N

3. The

××

PR (priority level) values do not affect the operation of

××

IF (interrupt request).

CPU processing

× ×

Instruction N

Instruction M

Save PSW and PC,
Jump to interrupt service

Interrupt service
program