Intel Pentium M 730 RH80536GE0252M User Manual
Product codes
RH80536GE0252M
Electrical Specifications
44
Mobile Intel
Pentium
4 Processor-M Datasheet
Figure 13. System Bus Reset and Configuration Timings
Figure 14. Source Synchronous 2X (Address) Timings
BCLK
Reset
Configuration
A[31:3], SMI#,
INIT#, BR[3:0]#
Valid
Tv = T13 (RESET# Pulse Width)
Tw = T45 (Reset Configuration Signals Setup TIme)
Tx = T46 (Reset Configuration Signals Hold TIme)
Tw = T45 (Reset Configuration Signals Setup TIme)
Tx = T46 (Reset Configuration Signals Hold TIme)
Tx
Tv
Tt
Tw
T
J
BCLK0
BCLK1
ADSTB# (@ driver)
A# (@ driver)
A# (@ receiver)
ADSTB# (@ receiver)
T1
T2
2.5 ns
5.0 ns
7.5 ns
T
H
T
H
T
J
T
N
T
K
T
M
valid
valid
valid
valid
T
H
= T23: Source Sync. Address Output Valid Before Address Strobe
T
J
= T24: Source Sync. Address Output Valid After Address Strobe
T
K
= T27: Source Sync. Input Setup to BCLK
T
M
= T26: Source Sync. Input Hold Time
T
N
= T25: Source Sync. Input Setup Time
T
P
= T28: First Address Strobe to Second Address Strobe
T
S
= T20: Source Sync. Output Valid Delay
T
R
= T31: Address Strobe Output Valid Delay
T
P
T
R
T
S