Intel Pentium M 730 RH80536GE0252M User Manual
Product codes
RH80536GE0252M
Electrical Specifications
Mobile Intel
Pentium
4 Processor-M Datasheet
47
Figure 18. Test Reset Timings
Figure 19. THERMTRIP# to Vcc Timing
Figure 20. FERR#/PBE# Valid Delay Timing
TRST#
PCB-773
1.25V
T
q
T
q
T37 (TRST# Pulse Width)
=
Tq = T64 (TRST# Pulse Width), V=0.5*Vcc
T38 (PROCHOT# Pulse Width), V=GTLREF
THERMTRIP#
Vcc
T39
T39 < 0.5 seconds
Note: THERMTRIP# is undefined when RESET# is active
Note: THERMTRIP# is undefined when RESET# is active
THERMTRIP#
Vcc
T39
T39 < 0.5 seconds
Note: THERMTRIP# is undefined when RESET# is active
Note: THERMTRIP# is undefined when RESET# is active
BCLK
STPCLK#
system bus
FERR#/
PBE#
SG
Ack
FERR#
undefined
FERR#
Ta
PBE#
undefined
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion)
Note: FERR#/PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system
bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE#
signal is driven. FERR# is driven at all other times.
bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE#
signal is driven. FERR# is driven at all other times.