Intel Pentium M 730 RH80536GE0252M User Manual

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Illustration of Deep Sleep VCC Static and Transient Tolerances (VID 
Setting = 1.30 V) ................................................................................................. 29

TCK Clock Waveform.......................................................................................... 41

System Bus Common Clock Valid Delay Timings............................................... 43

System Bus Reset and Configuration Timings.................................................... 44

Source Synchronous 2X (Address) Timings ....................................................... 44

Source Synchronous 4X Timings ........................................................................ 45

Power Up Sequence ........................................................................................... 46

Power Down Sequence....................................................................................... 46

BCLK Signal Integrity Waveform......................................................................... 52

Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers ................................................................................................................. 54

High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers ................................................................................................................. 54

The Coordinates of the Processor Pins as Viewed From the Top of the 
Package. ............................................................................................................. 65

Clock Control States............................................................................................ 94