Intel Pentium M 730 RH80536GE0252M User Manual
Product codes
RH80536GE0252M
Introduction
Mobile Intel
Pentium
4 Processor-M Datasheet
9
1.
Introduction
The Mobile Intel
Pentium
4 Processor-M is the first Intel mobile processor with the Intel
NetBurst
TM
micro-architecture. The Mobile Intel Pentium 4 Processor-M utilizes a 478-pin, Micro
Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a surface-mount, Zero Insertion
Force (ZIF) socket. The Mobile Intel Pentium 4 Processor-M maintains full compatibility with IA-
32 software. In this document the Mobile Intel Pentium 4 Processor-M will be referred to as the
“Mobile Intel Pentium 4 Processor-M” or simply “the processor.”
Force (ZIF) socket. The Mobile Intel Pentium 4 Processor-M maintains full compatibility with IA-
32 software. In this document the Mobile Intel Pentium 4 Processor-M will be referred to as the
“Mobile Intel Pentium 4 Processor-M” or simply “the processor.”
The Intel NetBurst micro-architecture features include hyper-pipelined technology, a rapid
execution engine, a 400-MHz system bus, and an execution trace cache. The hyper pipelined
technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor-M allowing the
processor to reach much higher core frequencies. The rapid execution engine allows the two
integer ALUs in the processor to run at twice the core frequency, which allows many integer
instructions to execute in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running
off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace
cache is a first level cache that stores approximately 12-k decoded micro-operations, which
removes the instruction decoding logic from the main execution path, thereby increasing
performance.
execution engine, a 400-MHz system bus, and an execution trace cache. The hyper pipelined
technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor-M allowing the
processor to reach much higher core frequencies. The rapid execution engine allows the two
integer ALUs in the processor to run at twice the core frequency, which allows many integer
instructions to execute in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running
off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace
cache is a first level cache that stores approximately 12-k decoded micro-operations, which
removes the instruction decoding logic from the main execution path, thereby increasing
performance.
Additional features within the Intel NetBurst micro-architecture include advanced dynamic
execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming
SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and
branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2
(L2) cache. A new floating point and multi media unit has been implemented which provides
superior performance for multi-media and mathematically intensive applications. Finally, SSE2
adds 144 new instructions for double-precision floating point, SIMD integer, and memory
management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, Deep Sleep,
and Deeper Sleep have been incorporated. The processor includes an address bus powerdown
capability which removes power from the address and data pins when the system bus is not in use.
This feature is always enabled on the processor.
execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming
SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and
branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2
(L2) cache. A new floating point and multi media unit has been implemented which provides
superior performance for multi-media and mathematically intensive applications. Finally, SSE2
adds 144 new instructions for double-precision floating point, SIMD integer, and memory
management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, Deep Sleep,
and Deeper Sleep have been incorporated. The processor includes an address bus powerdown
capability which removes power from the address and data pins when the system bus is not in use.
This feature is always enabled on the processor.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
The Mobile Intel Pentium 4 Processor-M’s 400-MHz Intel NetBurst micro-architecture system bus
utilizes a split-transaction, deferred reply protocol like the Intel Pentium 4 Processor. This system
bus is not compatible with the P6 processor family bus. The 400-MHz Intel NetBurst micro-
architecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 Gbytes/second.
utilizes a split-transaction, deferred reply protocol like the Intel Pentium 4 Processor. This system
bus is not compatible with the P6 processor family bus. The 400-MHz Intel NetBurst micro-
architecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 Gbytes/second.
The processor, when used in conjunction with the requisite Intel SpeedStep
technology applet or
its equivalent, supports Enhanced Intel SpeedStep technology, which enables real-time dynamic
switching of the voltage and frequency between two performance modes. This occurs by switching
the bus ratios, core operating voltage, and core processor speeds without resetting the system.
switching of the voltage and frequency between two performance modes. This occurs by switching
the bus ratios, core operating voltage, and core processor speeds without resetting the system.