Intel Celeron M 390 RH80536NC0291M Data Sheet

14

Datasheet

Since the AGTL+ signal pins receive power from the FSB, these pins should not be 

driven (allowing the level to return to V

CCP

) for minimum power drawn by the 

termination resistors in this state. In addition, all other input pins on the FSB should be 

driven to the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor stays in 

Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, and 

DPSLP# pins must be deasserted more than 480 µs prior to RESET# deassertion (AC 

Specification T45). When re-entering the Stop-Grant state from the Sleep state, 

STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# 

(AC Specification T75).

While in the Stop-Grant state, the processor services snoops and latch interrupts 

delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and 

services only upon return to the Normal state. 

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# is 

asserted if there is any pending interrupt or monitor event latched within the processor. 

Pending interrupts that are blocked by the EFLAGS.IF bit being clear still cause 

assertion of PBE#. Assertion of PBE# indicates to system logic that the processor 

should return to the Normal state.

A transition to the Stop Grant Snoop state occurs when the processor detects a snoop 

on the FSB (see 

). A transition to the Sleep state (see 

) 

occurs with the assertion of the SLP# signal.

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor stays in this state 

until the snoop on the FSB has been serviced (whether by the processor or another 

agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-

Grant state once the snoop has been serviced or the interrupt has been latched.

The Sleep state is a low-power state in which the processor maintains its context, 

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is 

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# 

pin should only be asserted when the processor is in the Stop-Grant state. SLP# 

assertions while the processor is not in the Stop-Grant state is out of specification and 

may result in unapproved operation. 

In the Sleep state, the processor is incapable of responding to snoop transactions or 

latching interrupt signals. No transitions or assertions of signals (with the exception of 

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep 

state. Snoop events that occur while in Sleep state or during a transition into or out of 

Sleep state causes unpredictable behavior. Any transition on an input signal before the 

processor has returned to the Stop-Grant state results in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as 

specified in the RESET# pin specification, then the processor resets itself, ignoring the 

transition through Stop-Grant state. If RESET# is driven active while the processor is in 

the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after 

RESET# is asserted to ensure the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power 

state, the Deep Sleep state, by asserting the DPSLP# pin. (See 

.) While 

the processor is in the Sleep state, the SLP# pin must be deasserted if another 

asynchronous FSB event needs to occur.