Intel X3370 INXEON3370 Data Sheet

Product codes

INXEON3370

Electrical Specifications

Datasheet

properly decouple the return currents from the front side bus. Bulk decoupling must

also be provided by the motherboard for proper [A]GTL+ bus operation. Decoupling

guidelines are described in the appropriate platform design guidelines.

2.3

Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage

Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop

LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage

to be delivered to the processor VCC lands (see

Chapter 2.7.3

for V

overshoot

specifications). Refer to

Table 2-11

for the DC specifications for these signals. Voltages

for each processor frequency is provided in

Table 2-3

NOTE: To support the Deeper Sleep State the platform must use a VRD 11.1 compliant

solution. The Deeper Sleep State also requires additional platform support. Refer to the

platform design guide and the Voltage Regulator-Down (VRD) 11.1 Processor Power

Delivery Design Guidelines for further details.

Individual processor VID values may be calibrated during manufacturing such that two

devices at the same core speed may have different default VID settings. This is

reflected by the VID Range values provided in

Table 2-3

. Refer to the Processor

Specification Update for further details on specific valid core frequency and VID values

of the processor. Note that this differs from the VID employed by the processor during

a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep

technology, or Extended HALT State).

The processor uses

eight

voltage identification signals, VID[

7:0

], to support automatic

selection of power supply voltages. Table 2-1 specifies the voltage level corresponding

to the state of VID[

7:0

]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers

to a low voltage level. If the processor socket is empty (VID[

7:0

] =

11111110

), or the

voltage regulation circuit cannot supply the voltage that is requested, it must disable

itself.

The processor provides the ability to operate while transitioning to an adjacent VID and

its associated processor core voltage (V

). This will represent a DC shift in the load

line. It should be noted that a low-to-high or high-to-low voltage state change may

result in as many VID transitions as necessary to reach the target core voltage.

Transitions above the specified VID are not permitted.

Table 2-3

includes VID step sizes

and DC shift ranges. Minimum and maximum voltages must be maintained as shown in

Table 2-4

and

Figure 2-1

as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD utilized must be capable of regulating its output to the value defined

by the new VID. DC specifications for dynamic VID transitions are included in

Table 2-3

and

Table 2-4

. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power

Delivery Design Guidelines For Desktop LGA775 Socket for further details.

Table 2-1.

Voltage Identification Definition

VID

Voltage

VID

Voltage

OFF

1.0375

1.6

1.025

1.5875

1.0125

1.575

1.5625

0.9875

1.55

0.975

1.5375

0.9625