Intel X3370 INXEON3370 Data Sheet

Product codes

INXEON3370

Datasheet

Introduction

The Quad-Core Intel® Xeon® Processor 3300 Series, like the Quad-Core Intel

Xeon

Processor 3200 Series, is a based on the Intel

Core

microarchitecture. The Intel

Core microarchitecture combines the performance of previous generation Desktop

products with the power efficiencies of a low-power microarchitecture to enable

smaller, quieter systems.The Quad-Core Intel® Xeon® Processor 3300 Series are 64-

bit processors that maintain compatibility with IA-32 software.

The processor utilizes Flip-Chip Land Grid Array (FC-LGA6) package technology, and

plug into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the

LGA775 socket.

Note:

In this document the Quad-Core Intel® Xeon® Processor 3300 Series may be referred

to simply as "the processor."

Note:

The Quad-Core Intel® Xeon® Processor 3300 Series refers to X3380, X3360, X3350,

X3330, X3320, L3360.

The processor is a quad-core processor, based on 45 nm process technology. The

processor features the Intel

Advanced Smart Cache, a shared multi-core optimized

cache that significantly reduces latency to frequently used data. The processors feature

a 1333 MHz front side bus (FSB) and either two independent but shared 6 MB of L2

cache (2x6M) or two independent but shared 3 MB of L2 cache (2x3M).The processor

supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD

Extensions 3 (SSE3), Supplemental Streaming SIMD Extension 3 (SSSE3), and the

Streaming SIMD Extensions 4.1 (SSE4.1). The processor supports several Advanced

Technologies: Execute Disable (XD) Bit, Intel

64 architecture (Intel

64), Enhanced

Intel SpeedStep

Technology, and Intel

Virtualization Technology (Intel

VT).

The processor's front side bus (FSB) utilizes a split-transaction, deferred reply protocol.

The FSB uses Source-Synchronous Transfer of address and data to improve

performance by transferring data four times per bus clock (4X data transfer rate).

Along with the 4X data bus, the address bus can deliver addresses two times per bus

clock and is referred to as a "double-clocked" or 2X address bus. Working together, the

4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.

The processor use some of the infrastructure already enabled by 2005 FMB platforms

including heatsink, heatsink retention mechanism, and socket. Manufacturability is a

high priority; hence, mechanical assembly may be completed from the top of the

baseboard and should not require any special tooling.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the active state when driven to a low level. For example, when RESET# is low, a reset

has been requested. Conversely, when NMI is high, a nonmaskable interrupt has

occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the ‘#’ symbol implies

that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front Side Bus” refers to the interface between the processor and system core logic

(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,

memory, and I/O.