Intel E5506 INXEONE5506 User Manual

Product codes

INXEONE5506

Intel® Xeon® Processors 5500 Series Electrical Specifications

Intel

Xeon

Processor 5500 Series Datasheet, Volume 1

DDR3 Command Signals

Single ended

CMOS Output

DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#,

DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0],

DDR{0/1/2}_BA[2:0], DDR{0/1/2}_MA_PAR

Single ended

Asynchronous Output

DDR{0/1/2}_RESET#

DDR3 Control Signals

Single ended

CMOS Output

DDR{0/1/2}_CS#[7:0], DDR{0/1/2}_ODT[5:0],

DDR{0/1/2}_CKE[3:0]

Single ended

Analog Input

DDR_VREF, DDR_COMP[2:0]

DDR3 Data Signals

Single ended

CMOS Input/Output

DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_ECC[7:0]

Differential

CMOS Input/Output

DDR{0/1/2}_DQS_[N/P][17:0]

Single ended

Asynchronous Input

DDR{0/1/2}_PAR_ERR#[2:0],

DDR_THERM#

Platform Environmental Control Interface (PECI)

Single ended

Asynchronous Input/Output

PECI

Processor Sideband Signals

Single ended

GTL Input/Output

BPM#[7:0], CAT_ERR#

Single ended

Asynchronous Input

PECI_ID#

Single ended

Asynchronous GTL Output

PRDY#, THERMTRIP#

Single ended

Asynchronous GTL Input

PREQ#

Single ended

Asynchronous GTL Input/Output

PROCHOT#

Single ended

Asynchronous CMOS Output

PSI#

Single ended

CMOS Output

VID[7:6],
VID[5:3]/CSC[2:0],
VID[2:0]/MSID[2:0],
VTT_VID[4:2]

System Reference Clock

Differential

Input

BCLK_DP, BCLK_DN

Test Access Port (TAP) Signals

Differential

CMOS Output

BCLK_ITP_DP, BCLK_ITP_DN

Single ended

Input

TCK, TDI, TMS, TRST#

Single ended

GTL Output

TDO

PWRGOOD Signals

Single ended

Asynchronous Input

CCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD

RESET Signal

Single ended

Asynchronous Input

RESET#

Power/Other Signals

Power / Ground

, V

CCPLL

, V

DDQ

TTA

, V

TTD

, V

Analog Input

COMP0, ISENSE

Sense Points

VCCSENSE, VSSSENSE, VSS_SENSE_VTTD,

VTTD_SENSE

Other

SKTOCC#, DBR#

Table 2-5.

Signal Groups (Sheet 2 of 2)

Signal Group

Buffer Type

Signals