Cisco CATALYST 3920 24 PORT TOKEN RING SWITCH Specification Guide
Introduction to the Catalyst 3920 1-9
Figure 1-3
Internal Components of the Catalyst 3920
CPU
The CPU performs all of the system initialization and switch table maintenance. It is an Intel 960SA
processor, operating at 16 MHz. It has 512 bytes of internal direct-mapped instruction cache and an
integrated interrupt controller.
processor, operating at 16 MHz. It has 512 bytes of internal direct-mapped instruction cache and an
integrated interrupt controller.
Program Memory DRAM
The program memory dynamic random-access memory (DRAM) is used for program and data
storage. It consists of four banks of DRAM providing up to 8 MB of storage.
storage. It consists of four banks of DRAM providing up to 8 MB of storage.
AXIS Bus
The architecture of the Catalyst 3920 centers around the AXIS bus, a 520 Mbps switching fabric
through which all switched ports communicate. The AXIS bus is a partially asynchronous time
division multiplexed bus used for switching packets between heterogeneous LAN modules.
through which all switched ports communicate. The AXIS bus is a partially asynchronous time
division multiplexed bus used for switching packets between heterogeneous LAN modules.
Quad Token Ring Port ASIC
The Quad Token Ring Port (QTP) ASIC interfaces directly to the Quad Media Access Controller
(QMAC) ASIC and provides the necessary functions for switching directly between the four Token
Ring ports connected to each QMAC, or between these and any other port within the switch.
(QMAC) ASIC and provides the necessary functions for switching directly between the four Token
Ring ports connected to each QMAC, or between these and any other port within the switch.
Quad Media Access Controller ASIC
The QMAC ASIC contains four protocol handlers to support four Token Ring physical connections
and interfaces directly to the QTP ASIC. It provides support for early token release (ETR) and FDX
operation, concentrator and adapter modes for dedicated Token Ring and normal operation, as well
as automatic mode detection.
and interfaces directly to the QTP ASIC. It provides support for early token release (ETR) and FDX
operation, concentrator and adapter modes for dedicated Token Ring and normal operation, as well
as automatic mode detection.
4 ports
4 ports
4 ports
4 ports
4 ports
QTP
QTP
QTP
QTP
QTP
QMAC
QMAC
QMAC
QMAC
QMAC
4 ports
QTP
QMAC
520 Mbps AXIS Bus
Stack port
Stack
xmit/recv
PFP
140 Mbps
FDX
I960
16 Mhz
8 Mb
DRAM
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