Intel X5672 AT80614005922AA User Manual

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command responses are prepended with a completion code that includes additional 
pass/fail status information. Refer to 

 for details regarding completion 

codes.

Note that the 4-byte PCI configuration address defined above is sent in standard PECI 
ordering with LSB first and MSB last.

The typical client response is a passing FCS, a passing Completion Code (CC) and valid 
Data. Under some conditions, the client’s response will indicate a failure.

The PCIConfigWr() command gives sideband write access to the PCI configuration 
space maintained in the processor. The exact listing of supported devices, functions is 
defined below in 

. PECI originators may conduct a device/function/register 

enumeration sweep of this space by issuing reads in the same manner that BIOS 
would.

Byte #

Byte 

Definition

0

Client Address

1

Write Length

0x05

2

Read Length

{0x02,0x03,0x05}

8

FCS

3

Cmd Code

0xc1

9

Completion

Code

10

Data 0

...

8+RL

Data N

9+RL

FCS

4

5

6

7

LSB

MSB

PCI Configuration Address

Abort FCS

Illegal command formatting (mismatched RL/WL/Command Code)

CC: 0x40

Command passed, data is valid

CC: 0x80

Error causing a response timeout. Either due to a rare, internal timing condition or a 

processor RESET or processor S1 state. Retry is appropriate outside of the RESET or 

S1 states.

2

1

Intel®

 

QuickPath Interconnect Link 0 Intel IBIST

2

5

Intel®

 

QuickPath Interconnect Link 1 Intel IBIST

3

4

Memory Controller Intel IBIST

1