Intel E5603 AT80614006954AA User Manual

45

1.

Used during initialization. It is the state of “OFF” condition for the transmitter. That is, when the output driver is disconnected 

and only the minimum termination is connected. The link detection resistor is assumed not connected when specifying this 

parameter.

2.

Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination is connected.

Z

RX_HIGH_CM_DC

Single ended DC impedance to GND for 

either D+ or D- of any data bit at Rx

10k

Ω

2

Z

TX_LINK_DETECT

Link Detection Resistor

500

2000

Ω

V

TX_LINK_DETECT

Link Detection Resistor Pull-up Voltage

1.6

V

T

DATA_TERM_SKEW

Skew between first to last data 

termination meeting Z

RX_LOW_CM_DC

128

UI

T

INBAND_RESET_SENSE

Time taken by inband reset detector to 

sense Inband Reset

1.5

µs

T

CLK_DET

Time taken by clock detector to observe 

clock stability

20k

UI

T

CLK_FREQ_DET

Time taken by clock frequency detector 

to decide slow vs. operational clock after 

stable clock

32

Reference 

Clock Cycles

T

Refclk-Tx-Variability

Phase variability between Reference Clk 

(at Tx input) and Tx output

500

psec

T

Refclk-jitter-rms-onepll

Accumulated rms jitter over n UI of a 

given PLL model output in response to 

the jittery reference clock input. The PLL 

output is generated by convolving the 

measured reference clock phase jitter 

with a given PLL transfer function. Here 

n=12.

0.5

psec

BER

Lane

Bit Error Rate per lane valid for 4.8, 5.86 

and 6.4 GT/s

1.0E-14

Events

QPI[1,0]_COMP

COMP Resistance

21.0-1%

21.0

21.0+1%

Ω

V

Tx-diff-pp-pin

Transmitter differential swing 

800

1400

mV

V

Tx-cm-dc-pin

Transmitter output DC common mode, defined as average 

of V

D+

 and V

D-

 Use setup of 

.

0.23

0.27

Fraction of 

V

TX-diff-pp-pin